Method and apparatus for high-efficiency operation of a dynamic random access memory

A data storage memory circuit comprising:

• a memory row having a plurality of memory cells, each memory cell connected to a word line and to one of a bit line or a complementary bit line,
• a column selector for selectively identifying one of the plurality of memory cells for a reading operation and a writing operation;
• and
• a sense amplifier for amplifying a charge to be stored in said memory cell during a writing operation, the sense amplifier including:
• an inverter circuit configured to pull up and pull down voltages of the bit line and the complementary bit line when writing the charge to the memory cell;
• and
• a controller configured to engage the inverter only when the charge is being written to the memory cell and to disengage the inverter of the sense amplifier when not writing the charge to the memory cell.

A sense amplifier circuit for use with a memory device comprising:

• an equalizer for driving a bit line and a complementary bit line to a common voltage;
• an inverter circuit configured to pull up and pull down voltages of the bit line and the complementary bit line when writing a charge to a memory cell;
• and
• a controller configured to engage the inverter when writing the charge to the memory cell and to disengage the inverter when not writing the charge to the memory cell.