Memory circuit including a resistive memory element and method for operating such a memory circuit
AssigneeInfineon Technologies AG
InventorsHeinz Hoenigschmid, Milena Dimitrova, Corvin Liaw, Michael Angerbauer
Life of this patent
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Abstract
The present invention relates to a memory circuit and method of operating the same. In at least one embodiment, the memory circuit includes a resistive memory element coupled to a plate potential by a first terminal; a bit line which is connectable to a second terminal of the resistive memory element; a programming circuit operable to change the resistance of the resistive memory element; a bleeder circuit operable to provide a bleeding current to or from the bit line due to a change of the resistance of the resistive memory element caused by the programming circuit.
Claims17
An integrated circuit, comprising:
- a resistive memory element coupled to a plate potential by a first terminal of the resistive memory element;
- a selection transistor having a first terminal coupled to a second terminal of the resistive memory element;
- a bit line coupled to a second terminal of the selection transistor and connectable to the resistive memory element via the selection transistor;
- a programming circuit operable to provide a programming voltage and to change a resistance of the resistive memory element during a programming operation, the programming circuit being connectable to the bit line and to the second terminal of the selection transistor via the bit line, wherein the programming circuit applies a programming signal via the bit line to the resistive memory element to transfer the resistive memory element into a low resistance state, and wherein the programming signal comprises at least one of a programming voltage and a programming current;
- and
- a regulator circuit coupled to the second terminal of the selection transistor and operable to provide a regulating current to or from the bit line to change a potential of the bit line in response to a change of the resistance of the resistive memory element caused by the programming circuit during the programming operation, wherein the regulator circuit and programming circuit are separately connectable to the bit line, wherein the regulator circuit comprises:
- a switch to selectively couple a regulator potential to the bit line depending on a regulate signal.
A memory circuit, comprising:
- a resistive memory element coupled to a plate potential by a first terminal of the resistive memory element;
- a bit line connectable to a second terminal of the resistive memory element;
- a programming circuit operable to provide a programming voltage to change a resistance of the resistive memory element during a programming operation, the programming circuit being connectable to the bit line;
- and
- a bleeder circuit connectable to the bit line and operable to provide a bleeding current to or from the bit line during the programming operation to change a potential on the bit line in response to a change of the resistance of the resistive memory element caused by the programming circuit during the programming operation;
- wherein the bleeder circuit comprises a dummy resistive memory element which is coupled to a bleeder potential with a first terminal of the dummy restrictive memory element and which is connectable to the bit line by a second terminal of the dummy restrictive memory element.
Dependencies are inferred from the claim text.