Nonvolatile ferroelectric memory device and refresh method thereof

A nonvolatile ferroelectric memory device comprising:

• a memory cell that comprises:
• a SOI-structured substrate including a floating channel layer and drain/source regions located at both ends of the floating channel layer;
• a ferroelectric layer formed over the floating channel layer;
• and
• a word line formed over the ferroelectric layer,
• wherein a different channel resistance is induced to a channel region of the floating channel layer depending on polarity states of the ferroelectric layer so that data are read/written;
• a register configured to temporarily store data read from the memory cell;
• a refresh information register configured to store nonvolatile parameter information for a refresh passing time and a refresh cycle and generate a refresh control signal by using the refresh passing time and the refresh cycle;
• and
• a refresh control unit configured to perform a refresh operation in response to the refresh control signal so as to write data stored in the register to the memory cell.

A nonvolatile ferroelectric memory device comprising:

• a cell array including a plurality of nonvolatile memory cells each configured to read/write data;
• a register configured to temporarily store data read from the plurality of nonvolatile memory cells;
• a refresh information register configured to store nonvolatile parameter information for a refresh passing time and refresh cycle and generate a refresh control signal by using the refresh passing time and the refresh cycle;
• a refresh control unit configured to control a refresh operation in response to the refresh control signal so as to write data stored in the register to one or more of the plurality of nonvolatile memory cells;
• a row address control unit configured to latch and decode a row address in response to a RAS signal and an output signal from the refresh control unit and to select the count address in the refresh mode;
• a column address control unit configured to latch and decode a column address inputted in response to a CAS signal;
• and
• an input/output logic circuit configured to control read/write operations of the cell array in response to an output enable signal and read/write commands.

A nonvolatile ferroelectric memory device comprising:

• a cell array including a plurality of nonvolatile memory cells each configured to read/write data;
• a register configured to temporarily store data read from the plurality of nonvolatile memory cells;
• a refresh information register configured to store nonvolatile parameter information for a refresh passing time and a refresh cycle and generate a refresh control signal by using the refresh passing time and the refresh cycle;
• a refresh control unit configured to activate a refresh signal in response to a RAS signal, a GAS signal and the refresh control signal;
• a refresh counter configured to generate a count address in response to the refresh signal;
• and
• a column timing logic circuit configured to write data stored in a register in the memory cell corresponding to the count address.

A method for refreshing a nonvolatile ferroelectric memory device, the method comprising the steps of:

• reading/writing data in a memory cell which has a 1T-FET type nonvolatile cell structure;
• storing nonvolatile parameter information for a refresh passing time and a refresh cycle and generating a refresh control signal by using the refresh passing time and the refresh cycle;
• and
• refreshing data of the memory cell in response to the refresh control signal.

A method for refreshing a nonvolatile ferroelectric memory device, the method comprising the steps of:

• sensing input of a RAS signal;
• sensing input of a GAS signal;
• activating a refresh signal in response to the RAS signal and the GAS signal;
• generating a count address in response to the refresh signal;
• storing nonvolatile parameter information for a refresh passing time and a refresh cycle and generating a refresh control signal by using the refresh passing time and the refresh cycle;
• and
• refreshing data of a memory cell in response to the refresh control signal by writing data stored in a register in the memory cell corresponding to the count address.