Thin film transistor array panel for liquid crystal display and method for manufacturing the same

A liquid crystal display comprising:

• a substrate;
• a first signal line assembly formed over the substrate, wherein the first signal line assembly comprises a first signal line, a first pad connected to the first signal line, a gate electrode connected to the first signal line, and a conductive electrode;
• a first nitrogen containing layer formed on the first signal line, the first pad, the gate electrode and the conductive electrode of the first signal line assembly to reduce formation of a high resistance oxide layer on the first signal line assembly;
• a second signal line assembly formed with a lower layer and an upper layer comprising a second signal tine intersecting and insulated from the first signal tine, a second pad, a source electrode, a drain electrode and a conductive pattern;
• a second nitrogen containing layer formed on the second signal line, the second pad, the source electrode, the drain electrode and the conductive pattern of the second signal line assembly, wherein the second nitrogen containing layer reduces formation of a high resistance oxide layer on the second signal line assembly;
• and
• a pixel electrode formed over a protective layer, the pixel electrode being electrically connected to the second signal line assembly,
• wherein the first and second nitrogen containing layers comprise one of an aluminum nitride layer, an aluminum alloy nitride layer, and an aluminum/neodymium alloy nitride layer.

A thin film transistor array panel, comprising:

• a substrate;
• a gate line assembly formed on the substrate, the gate line assembly including a gate line, gate pad, gate electrode and conductive electrode;
• a first low resistance conductive layer formed on the gate line, gate pad, gate electrode and conductive electrode;
• a gate insulating layer formed on the first low resistance conductive layer and the substrate;
• a semiconductor pattern formed on the gate insulating layer;
• an ohmic contact pattern formed on the semiconductor pattern;
• a data line assembly formed on the ohmic contact pattern, the data line assembly including a data line, data pad, source electrode, drain electrode and conductive pattern;
• a second low resistance conductive layer formed on the data line, data pad, source electrode, drain electrode and conductive pattern;
• a protective layer formed on the second low resistance conductive layer and the gate insulating layer, the protective layer having a first contact hole exposing a portion of the second low resistance conductive layer on the conductive pattern and a second contact hole exposing a portion of the second low resistance conductive layer on the drain electrode;
• and
• a pixel electrode formed on the protective layer, the pixel electrode electrically connected to the drain electrode through the second contact hole and the conductive pattern through the first contact hole.

A thin film transistor array panel, comprising:

• a substrate;
• a gate line assembly formed on the substrate, the gate line assembly including a gate pad, a gate electrode, a gate line and a conductive electrode;
• a first low resistance conductive layer including aluminum nitride, aluminum alloy nitride or aluminum/neodymium alloy nitride being formed on the gate pad, the gate electrode, the gate line and the conductive electrode;
• a gate insulating layer formed on the first low resistance conductive layer and the substrate;
• a data line assembly formed on the gate insulating layer, the data line assembly including a data line, a data pad, a source electrode, a drain electrode and a conductive pattern;
• a protective layer formed on the data line assembly and the gate insulating layer, the protective layer having a first contact hole exposing the drain electrode;
• and
• a pixel electrode formed on the protective layer, the pixel electrode being electrically connected to the drain electrode through the first contact hole.