Display controller
AssigneeIntel Corporation
InventorsJames P. Kardach, David Williams, Achintya K. Bhowmik, Barnes Cooper
Life of this patent
Estimating the term…
Abstract
Apparatus and systems, as well as methods and articles, may operate to update video display pixels. A video display bus can communicate data to a video display according to specified clock frequencies and a refresh time period. Power conservation can be enhanced by adjusting the specified clock frequencies and/or refresh time period to provide idle time on the video display bus.
Claims16
An apparatus comprising:
- a controller to update pixel data of a display during a display refresh time, wherein the controller is to communicate a content of a buffer to the display at a clock frequency via a display bus, wherein the buffer is to be loaded from a memory via a memory bus, and wherein the controller is to increase the clock frequency to provide increased idle time on the memory bus and on the display bus, the increased idle time on the memory bus to enable a self-refresh time of the memory to be increased, and the increased idle time on the display bus to enable one or more of the display bus and logic of the controller to be powered-down.
A system comprising:
- a processor;
- a memory;
- a frame buffer coupled to the memory;
- a liquid crystal video display;
- and
- a graphics controller coupled to the processor and the frame buffer, the graphics controller to update the video display from the frame buffer according to a display refresh rate, wherein the graphics controller is coupled to communicate a content of the frame buffer to the video display at a clock frequency via a display bus, wherein the frame buffer is to be loaded from the memory via a memory bus;
- wherein the processor is to provide instructions to the graphics controller to increase the clock frequency to provide increased idle time on the memory bus and on the display bus, the increased idle time on the memory bus to enable a self-refresh time of the memory to be increased, and the increased idle time on the display bus to enable one or more of the display bus and logic of the controller to be powered-down.
A method comprising:
- transferring data from a memory to a buffer via a memory bus;
- updating a video display from the buffer according to a display refresh rate via a display bus;
- and
- increasing a clock frequency of data communicated on the memory bus and on the display bus to provide increased idle time on the memory bus and on the display bus, the increased idle time on the memory bus to enable a self-refresh time of the memory to be increased, and the increased idle time on the display bus to enable one or more of the display bus and logic of the controller to be powered-down.
A machine-accessible medium having associated information, wherein the information, when accessed, results in a machine performing:
- transferring data from a memory to a buffer via a memory bus;
- updating a video display from the buffer according to a display refresh rate via a display bus;
- detecting video display inactivity;
- and
- in response to the detected video display inactivity selectively adjusting the updating of the video display to provide increased idle time on the memory bus and on the display bus, wherein selectively adjusting the updating of the video display comprises adjusting the refresh rate and increasing a clock frequency of data communicated on the memory bus and on the display bus, the increased idle time on the memory bus to enable a self-refresh time of the memory to be increased, and the increased idle time on the display bus to enable the display bus to be powered-down.
Dependencies are inferred from the claim text.