Current-controlled CMOS (C3MOS) fully differential integrated wideband amplifier/equalizer with adjustable gain and frequency response without additional power or loading

A current-controlled CMOS (C3MOS) wideband data amplifier/equalizer circuit having adjustable gain and frequency response, the circuit comprising:

• a first differential transistor comprising a source, gate, and drain;
• a second differential transistor comprising a source, gate, and drain;
• a first current source that is coupled to the source of the first differential transistor;
• a second current source that is coupled to the source of the second differential transistor;
• a first output impedance, comprising a first output resistor and a first shunt peaking inductor connected in series, that is coupled between the drain of the first differential transistor and a supply voltage;
• a second output impedance, comprising a second output resistor and a second shunt peaking inductor connected in series, that is coupled between the drain of the second differential transistor and the supply voltage;
• and
• a switchable RC network, comprising a resistor and a capacitor connected in parallel, that is coupled between the source of the first differential transistor and the source of the second differential transistor;
• and wherein:
• the switchable RC network is operable to select an impedance from a plurality of impedances between the source of the first differential transistor and the source of the second differential transistor.

A current-controlled CMOS (C3MOS) wideband data amplifier/equalizer circuit having adjustable gain and frequency response, the circuit comprising:

• a first differential transistor comprising a source, gate, and drain;
• a second differential transistor comprising a source, gate, and drain;
• a first current source that is coupled to the source of the first differential transistor;
• a second current source that is coupled to the source of the second differential transistor;
• a first output impedance, comprising a first output resistor and a first shunt peaking inductor connected in series, such that the first output resistor is coupled between the drain of the first differential transistor and the first shunt peaking inductor, and the first shunt peaking inductor is coupled between the first output resistor and a supply voltage;
• a second output impedance, comprising a second output resistor and a second shunt peaking inductor connected in series, such that the second output resistor is coupled between the drain of the second differential transistor and the second shunt peaking inductor, and the second shunt peaking inductor is coupled between the second output resistor and the supply voltage;
• a first series inductor that is coupled between a first differential input of the C3MOS wideband data amplifier circuit and the gate of the first differential transistor;
• and
• a second series inductor that is coupled between a second differential input of the C3MOS wideband data amplifier circuit and the gate of the second differential transistor;
• a first capacitor that is coupled between the drain of the first differential transistor and the gate of the second differential transistor;
• a second capacitor that is coupled between the drain of the second differential transistor and the gate of the first differential transistor;
• and
• a switchable RC network, comprising a variable resistor and a variable capacitor connected in parallel, that is coupled between the source of the first differential transistor and the source of the second differential transistor.