Semiconductor integrated circuit apparatus and electronic apparatus

A semiconductor integrated circuit apparatus, comprising:

• a logic circuit having a plurality of NchMIS transistors and a plurality of PchMIS transistors;
• a first pseudo power supply line coupled to a high potential side power supply terminal section of the logic circuit;
• a second pseudo power supply line coupled to a low potential side power supply terminal section of the logic circuit;
• and
• a first PchMIS transistor formed on a silicon substrate of a silicon-on-insulator structure, wherein:
• the first pseudo power supply line is connected to a drain of the first PchMIS transistor;
• a high potential side power supply line is connected to a source of the first PchMIS transistor;
• a gate of the first PchMIS transistor and the substrate are connected through a current limiter;
• an absolute value of a threshold voltage of the first PchMIS transistor does not exceed an absolute value of a threshold voltage of the MIS transistors of the logic circuit, or the first PchMIS transistor is a depletion type;
• and
• a high level of a signal applied to the gate of the first PchMIS transistor is higher than a potential of the high potential side power supply line.

A semiconductor integrated circuit apparatus, comprising:

• a logic circuit having a plurality of NchMIS transistors and a plurality of PchMIS transistors;
• a first pseudo power supply line coupled to a high potential side power supply terminal section of the logic circuit;
• a second pseudo power supply line coupled to a low potential side power supply terminal section of the logic circuit;
• a first NchMIS transistor which has a threshold voltage which does not exceed an absolute value of a threshold voltage of the MIS transistors of the logic circuit or which is a depletion type;
• and
• a second NchMIS transistor which has a threshold voltage which does not exceed the absolute value of the threshold voltage of the MIS transistors of the logic circuit or which is the depletion type, wherein:
• a source of the second NchMIS transistor is connected to a drain of the first NchMIS transistor;
• the second pseudo power supply line is connected to a drain of the second NchMIS transistor;
• a low potential side power supply line is connected to a source of the first NchMIS transistor;
• and
• a substrate of the first NchMIS transistor and a substrate of the second NchMIS transistor are coupled to a gate of the second NchMIS transistor.

A semiconductor integrated circuit apparatus, comprising:

• a logic circuit having a plurality of NchMIS transistors and a plurality of PchMIS transistors;
• a first pseudo power supply line connected to a high potential side power supply terminal section of the logic circuit;
• a second pseudo power supply line connected to a low potential side power supply terminal section of the logic circuit;
• a first NchMIS transistor which has a threshold voltage which does not exceed an absolute value of a threshold voltage of the MIS transistors of the logic circuit or which is a depletion type;
• and
• a second NchMIS transistor which has a threshold voltage which does not exceed the absolute value of the threshold voltage of the MIS transistors of the logic circuit or which is the depletion type, wherein:
• a source of the second NchMIS transistor is connected to a drain of the first NchMIS transistor;
• the second pseudo power supply line is connected to a drain of the second NchMIS transistor;
• a low potential side power supply line is connected to a source of the first NchMIS transistor;
• and
• a substrate of the first NchMIS transistor and a substrate of the second NchMIS transistor are coupled to a gate of the first NchMIS transistor.

A semiconductor integrated circuit apparatus, comprising:

• a logic circuit having a plurality of NchMIS transistors and a plurality of PchMIS transistors;
• a first pseudo power supply line connected to a high potential side power supply terminal section of the logic circuit;
• a second pseudo power supply line connected to a low potential side power supply terminal section of the logic circuit;
• a first PchMIS transistor which has a threshold voltage which does not exceed an absolute value of a threshold voltage of the MIS transistors of the logic circuit or which is a depletion type;
• and
• a second PchMIS transistor which has a threshold voltage which does not exceed the absolute value of the threshold voltage of the MIS transistors of the logic circuit or which is the depletion type, wherein
• a source of the second PchMIS transistor is connected to a drain of the first PchMIS transistor;
• the first pseudo power supply line is connected to a drain of the second PchMIS transistor;
• a high potential side power supply line is connected to a source of the first PchMIS transistor;
• and
• a substrate of the first PchMIS transistor and a substrate of the second PchMIS transistor are coupled to a gate of the second PchMIS transistor.

A semiconductor integrated circuit apparatus, comprising:

• a logic circuit having a plurality of NchMIS transistors and a plurality of PchMIS transistors;
• a first pseudo power supply line connected to a high potential side power supply terminal section of the logic circuit;
• a second pseudo power supply line connected to a low potential side power supply terminal section of the logic circuit;
• a first PchMIS transistor which has a threshold voltage which does not exceed an absolute value of a threshold voltage of the MIS transistors of the logic circuit or which is a depletion type;
• and
• a second PchMIS transistor which has a threshold voltage which does not exceed the absolute value of the threshold voltage of the MIS transistors of the logic circuit or which is the depletion type, wherein:
• a source of the second PchMIS transistor is connected to a drain of the first PchMIS transistor;
• the first pseudo power supply line is connected to a drain of the second PchMIS transistor;
• a high potential side power supply line is connected to a source of the first PchMIS transistor;
• and
• a substrate of the first PchMIS transistor and a substrate of the second PchMIS transistor are coupled to a gate of the first PchMIS transistor.