Semiconductor integrated apparatus using two or more types of power supplies

A semiconductor integrated apparatus, comprising:

• a control circuit unit which is connected to a low potential power supply terminal and a ground potential power supply terminal, and to which a low potential power supply output is supplied from an external point of the apparatus via the low potential power supply terminal;
• an output circuit unit which is connected to a high potential power supply terminal and the ground potential power supply terminal and which has an output level controlled based on control data, the high potential power supply terminal being having a high potential power supply output higher than the low potential power supply output;
• a detection circuit unit which has a test terminal, is connected to the low potential power supply terminal, and detects a decline in the low potential power supply output;
• and
• a level shifter circuit which is connected between the control circuit unit and the output circuit unit and which controls the output level of the output circuit unit in response to a detected output from the detection circuit unit,
• wherein the detection circuit unit includes a NOR circuit whose output becomes low in level when the low potential power supply output decreases to a value smaller than a predetermined value or when a test signal is supplied to the test terminal,
• wherein the level shifter circuit includes:
• a cross-link circuit to which the high potential power supply output is supplied and which includes first and second P-channel metal oxide semiconductor (PMOS) transistors;
• an amplifying circuit to which the cross-link circuit is a load and which includes first and second N-channel metal oxide semiconductor (NMOS) transistors;
• a switch which is serially connected in series with the amplifying circuit and which is controlled in accordance with a detection output of the detection circuit unit so as to turn on or turn off a path between the cross-link circuit and a ground potential, the switch including third and fourth NMOS transistors;
• first and second inverter circuits which generate clock signals in response to an off state of the third and fourth NMOS transistors;
• and
• a clocked inverter circuit which is responsive to the clock signals supplied from the first and second inverter circuits and retains the control data to keep the output level of the output circuit unit in a state assumed before the low potential power supply output decreases.