Clock synthesis using polyphase numerically controlled oscillator
AssigneeAltera Corporation
InventorsBenjamin Esposito, Hong Shan Neoh
Life of this patent
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Abstract
A clock synthesis circuit includes a polyphase numerically controlled oscillator, an extraction circuit, and a clock signal generation circuit. The polyphase numerically controlled oscillator generates sets of periodic output signals. Each set of the periodic output signals represents a different phase of a periodic waveform signal. The extraction circuit extracts a most significant bit from each set of the periodic output signals of the polyphase numerically controlled oscillator to generate most significant bits. The clock signal generation circuit converts the most significant bits into a serial bit stream that serves as an output clock signal.
Claims20
A circuit comprising:
- a polyphase numerically controlled oscillator that generates sets of periodic output signals, wherein each set of the periodic output signals represents a different phase of a periodic waveform signal;
- an extraction circuit that extracts a most significant bit from each set of the periodic output signals of the polyphase numerically controlled oscillator to generate most significant bits;
- and
- a clock signal generation circuit that converts the most significant bits into a bit stream to generate an output clock signal.
A system comprising:
- a polyphase numerically controlled oscillator generating sets of periodic output signals in parallel in response to an input clock signal, wherein each of the sets of periodic output signals represents a different phase of a periodic sinusoidal signal;
- an extraction circuit that extracts a most significant bit from each of the sets of periodic output signals of the polyphase numerically controlled oscillator and outputs the most significant bits in parallel;
- and
- a serializer that performs a parallel-to-serial conversion on the most significant bits output by the extraction circuit to generate a serial bit stream, wherein the serial bit stream forms an output clock signal.
A method for generating a clock signal, the method comprising:
- generating sets of periodic output signals using a polyphase numerically controlled oscillator, wherein each set of the periodic output signals represents a different phase of a periodic waveform signal;
- extracting a most significant bit from each set of the periodic output signals of the polyphase numerically controlled oscillator to generate most significant bits;
- and
- converting the most significant bits into a serial bit stream that forms an output clock signal.
Dependencies are inferred from the claim text.