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US 7,598,786 B2Granted
Duty cycle correction circuit and method thereof
AssigneeNanya Technology Corporation
InventorWen-Chang Cheng
Life of this patent
Estimating the term…
Abstract
A duty cycle correction circuit comprises a frequency divider, a duty cycle detector and a delay circuit. The frequency divider receives a first clock signal and divides the frequency of the first clock signal to generate a second clock signal. The duty cycle detector receives the second clock signal and a correction clock signal and generates a control signal according to the second clock signal and the correction clock signal. The delay circuit receives the first clock signal and the control signal and adjusts a delay time of a falling edge of the first clock signal according to the control signal to generate the correction clock.
Claims14
A duty cycle correction circuit, comprising
- a frequency divider receiving a first clock signal and dividing frequency of the first clock signal to generate a second clock signal;
- a duty cycle detector receiving the second clock signal and a correction clock signal and generating a control signal according to the second clock signal and the correction clock signal, wherein the duty cycle detector comprises:
- a first fixed current source generating a first current;
- a second fixed current source generating a second current, wherein the second current is double the first current;
- a first switch coupled to the first fixed current source and turned on or off according to the second clock signal;
- a second switch coupled to the second fixed current source and turned on or off according to the correction clock signal;
- a third switch coupled between the first switch and a ground and turned on or off according to an inverting correction clock signal;
- a fourth switch coupled between the second switch and the ground and turned on or off according to the inverting correction clock signal;
- and
- a comparator receiving the first current and the second current, respectively converting the first current and the second current to a first voltage and a second voltage, and comparing the first voltage and the second voltage to generate an output signal through a fifth switch to charge a capacitor to generate the control signal;
- and
- a delay circuit receiving the first clock signal and the control signal and adjusting a delay time of a falling edge of the first clock signal according to the control signal to generate the correction clock.
9 more elements
A duty cycle correction method, comprising:
- dividing a frequency of a first clock signal to generate a second clock signal;
- charging a first terminal of a comparator by a first fixed current during a period of the first clock signal;
- charging a second terminal of the comparator by a second fixed current during the period of the first clock signal;
- comparing voltages of the first terminal and the second terminal of the comparator to generate a control signal;
- and
- adjusting a delay time of a falling edge of the first clock signal according to the control signal.
3 more elements
A duty cycle correction circuit, comprising
- a frequency divider receiving a first clock signal and dividing frequency of the first clock signal to generate a second clock signal;
- a duty cycle detector receiving the second clock signal and a correction clock signal and generating a control signal according to the second clock signal and the correction clock signal;
- and
- a delay circuit receiving the first clock signal and the control signal and adjusting a delay time of a falling edge of the first clock signal according to the control signal to generate the correction clock, wherein the delay circuit comprises:
- an inverting circuit inverting the first clock signal to generate a first output signal;
- a first delay line circuit receiving the first output signal and delaying the first output signal by a first delay time to output a first delay output signal;
- a second delay line circuit receiving the first output signal and delaying the first input signal by a second delay time according to the control signal to output a second delay output signal;
- an inverter inverting the first input signal to output a switch control signal;
- a first tri-inverter receiving the first delay output signal and outputting a first output signal according to the switch control signal;
- a second tri-inverter receiving the second delay output signal and outputting a second output signal according to the switch control signal;
- a first inverting circuit inverting the first output signal or the second output signal to output an inverting output signal;
- and
- a second inverting circuit inverting the inverting output signal to output the correction clock signal.
10 more elements
Dependencies are inferred from the claim text.