DLL circuit and method of controlling the same
AssigneeHynix Semiconductor Inc.
InventorsDong-Suk Shin, Hyun-Woo Lee, Won-Joo Yun
Life of this patent
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Abstract
A DLL circuit includes a duty ratio detection unit that detects a duty ratio of a rising clock and a duty ratio of a falling clock, thereby outputting a duty ratio detection signal. A correction control unit generates a correction control signal in response to the duty ratio detection signal. A duty ratio correction unit corrects a duty ratio of an internal. clock in response to the correction control signal, thereby outputting a reference clock.
Claims64
A DLL (Delay Locked Loop) circuit comprising:
- a duty ratio detection unit configured to detect a duty ratio of a rising clock and a duty ratio of a falling clock and output a duty ratio detection signal;
- a correction control unit configured to receive the duty ratio detection signal and generate a correction control signal in response to the duty ratio detection signal and, if a logical value of the correction control signal reaches a limit value, to enable a mixing enable signal;
- and
- a duty ratio correction unit configured to receive the correction control signal, correct a duty ratio of an internal clock in response to the correction control signal, and output a reference clock.
A DLL circuit comprising:
- a duty ratio correction unit configured to receive a rising clock and a falling clock, correct a duty ratio of an internal clock according to a duty ratio of the rising clock and a duty ratio of a falling clock, and output a reference clock;
- and
- a phase mixing unit configured receive the rising clock and the falling clock and selectively mix a phase of the rising clock and a phase of the falling clock according to whether or not an operation frequency of the duty ratio correction unit is limited.
A method of controlling a DLL circuit, the method comprising:
- detecting a duty ratio of a rising clock and a duty ratio of a falling clock;
- outputting a duty ratio detection signal based on the detecting the duty ratio;
- generating a correction control signal in response to the duty ratio detection signal and, if a logical value of the correction control signal reaches a limit value, enabling a mixing enable signal;
- correcting a duty ratio of an internal clock in response to the correction control signal;
- and
- outputting a reference clock based on the correcting the duty ratio.
A method of controlling a DLL circuit, the method comprising:
- correcting a duty ratio of an internal clock according to a duty ratio of a rising clock and a duty ratio of a falling clock;
- outputting a reference clock based on the correcting the duty ratio;
- and
- selectively mixing the rising clock and the falling clock according to whether or not an operation frequency to correct the duty ratio of the internal clock is limited.
Dependencies are inferred from the claim text.