US 7,598,774 B2 · Reduced power consumption limited-switch dynamic logic (LSDL) circuit

Abstract

An limited-switch dynamic logic (LSDL) circuit provides reduced power consumption by reducing clock power dissipation. By clocking LSDL gates with a clock signal having a reduced voltage swing in the evaluation phase, the LSDL gates are permitted to operate, while reducing the clock power consumption dramatically. Since clock power consumption dominates in LSDL circuits, the reduction in clock power dissipation results in a significant reduction in overall circuit power consumption. The reduced swing clock is produced at a plurality of local clock buffers by supplying the local clock buffers with an extra power supply rail that is switched onto the clock distribution lines by the local clock buffers in response to the full-swing evaluate phase clock received from the global clock distribution network by the local clock buffers.

Claims11

Dependent claims

An integrated circuit comprising:

a plurality of dynamic logic circuits each having a clock input for controlling evaluation and pre-charging of a summing node and a plurality of logic inputs for determining whether or not to said evaluation in response to said clock changes a logical state of said summing node;
and
a local clock buffer having a clock output connected to said clock input of each of said plurality of dynamic logic circuits, and wherein said local clock buffer includes a reduced-swing clock generator circuit having an output connected for generating a reduced-swing clock signal having an evaluate phase voltage state substantially differing from a voltage of a first power supply rail of said plurality of dynamic circuits and a pre-charge voltage state substantially equal to a voltage of a second power supply rail of said plurality of dynamic circuits.

An integrated circuit comprising:

a plurality of dynamic logic circuits each having
a dynamic logic tree for discharging a summing node in response to predetermined states of one or more logical input signals connected to inputs of said dynamic logic tree,
at least one input foot device having a gate connected to said clock signal for isolating said dynamic logic tree from said second power supply rail during said pre-charge phase,
a first inverter having an input connected to said summing node and including an inverter foot device for isolating said first inverter from said second power supply rail during said pre-charge phase,
a second inverter having an input connected to an output of said first inverter and an output for providing an output of said dynamic logic gates, and
a keeper circuit for holding a state said output of said first inverter when said clock signal is in said pre-charge phase, and wherein said keeper has a disable device having an input connected to said clock signal for disabling said keeper during said evaluate phase of said clock, and wherein said disable device is disabled during said evaluation phase of said clock with said evaluate phase voltage;
and
a local clock buffer having a clock output connected to said clock input of each of said plurality of dynamic logic circuits, and wherein said local clock buffer includes a reduced-swing clock generator circuit having an output connected for generating a reduced-swing clock signal having an evaluate phase voltage state substantially differing from a voltage of a first power supply rail of said plurality of dynamic circuits and a pre-charge voltage state substantially equal to a voltage of a second power supply rail of said plurality of dynamic circuits.

5 more elements

Dependencies are inferred from the claim text.

Reduced power consumption limited-switch dynamic logic (LSDL) circuit

Life of this patent

Reduced power consumption limited-switch dynamic logic (LSDL) circuit

Life of this patent

Abstract

Claims11