Level shifter for gate driver

A level shifter, wherein multiple stages of the level shifters are suitable to be serially-connected into a gate drive circuit, each stage comprising an output end coupled to an input end of a next stage level shifter, and a reset end for receiving an output signal of the next stage level shifter, the level shifter comprising:

• a first node and a second node;
• a driving transistor, provided with a gate, a source, and a drain, wherein the gate is coupled to the first node, the drain is coupled to a clock signal, and the source is coupled to an output signal;
• a reset transistor, provided with a gate, a source, and a drain, wherein the gate receives the output signal of the next stage level shifter as a reset signal, the source is coupled to a first low-potential voltage, and the drain is coupled to the second node;
• a charge/discharge circuit, for receiving an input signal and a control signal, and coupled to a high-potential voltage, a second low-potential voltage, and the second node;
• a threshold voltage detector, for receiving the control signal, and coupled to the first node and the source of the driving transistor;
• and
• a memory capacitor, provided with a first end and a second end respectively coupled to the first node and the second node, for memorizing a threshold voltage of the driving transistor.

A level shifter, wherein multiple stages of the level shifters are suitable to be serially-connected into a gate drive circuit, each comprising an output end coupled to an input end of a next stage level shifter, and a reset end for receiving an output signal of the next stage level shifter, the level shifter comprising:

• a first node and a second node;
• a driving transistor, provided with a gate, a source, and a drain, wherein the gate is coupled to the first node, the drain is coupled to a clock signal, and the source functioning as the output end outputs an output signal;
• a reset transistor, provided with a gate, a source, and a drain, wherein the gate receives the output signal of the next stage level shifter as a reset signal, the source is coupled to a first low-potential voltage, and the drain is coupled to the first node;
• a charge/discharge circuit, used for receiving an input signal, a first control signal, and a second control signal, and coupled to a second low-potential voltage and the second node;
• a threshold voltage detector, used for receiving the first control signal and the second control signal, and coupled to the first node and the source of the driving transistor;
• and
• a memory capacitor, provided with a first end and a second end respectively coupled to the first node and the second node, for memorizing a threshold voltage of the driving transistor.

A level shifter, wherein multiple stages of the level shifters are suitable to be serially-connected into a gate drive circuit, each stage comprising an output end coupled to an input end of a next stage level shifter, and a reset end for receiving an output signal of the next stage level shifter, the level shifter comprising:

• a first node and a second node;
• a driving transistor, provided with a gate, a source, and a drain, wherein the gate is coupled to the first node, the drain is coupled to a clock signal, and the source functioning as the output end outputs an output signal;
• a reset transistor, provided with a gate, a source, and a drain, wherein the gate receives the output signal of the next stage level shifter as a reset signal, the source is coupled to a low-potential voltage, and the drain is, coupled to the first node;
• a charge circuit, for receiving an input signal, and coupled to the second node;
• a threshold voltage detector, for receiving the control signal, and coupled to the first node, the second node, and the source of the driving transistor;
• and
• a memory capacitor, provided with a first end and a second end respectively coupled to the first node and the second node, for memorizing a threshold voltage of the driving transistor.