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US 7,598,767 B1Granted
Multi-standard data communication interface circuitry for programmable logic devices
AssigneeAltera Corporation
InventorNing Xue
Life of this patent
Estimating the term…
Abstract
A programmable logic device includes a hard IP portion, which includes circuitry that is dedicated to receiving a high-speed serial data signal and performing certain basic functions related to byte alignment on that data signal, and a more general-purpose programmable logic portion. The programmable logic portion is used for such tasks as synchronizing the byte-aligned data in accordance with any one of a number of possible data communication protocols.
Claims21
Programmable logic device integrated circuitry comprising:
- hard IP circuitry including circuitry for receiving a serial data signal, making a number of successive bits of the serial data signal available in parallel, and selecting aligned bytes of data from the parallel bits;
- and
- general-purpose programmable logic circuitry that is configurable, in use, to receive the aligned bytes from the hard IP circuitry and to synchronize the aligned bytes in accordance with communication protocol parameters that are programmed into the programmable logic circuitry,
- wherein the hard IP circuitry further includes:
- first circuitry for detecting whether or not an aligned byte corresponds to a valid byte code,
- second circuitry for applying an output signal of the first circuitry to the programmable logic circuitry, and
- third circuitry that is selectively responsive to the output signal of the first circuitry for selecting which of the parallel bits will be tried as aligned bytes,
- and wherein the third circuitry is responsive to a signal from the programmable logic circuitry with regard to how the third circuitry responds to the output signal of the first circuitry,
- the programmable logic circuitry being configurable to base the signal from the programmable logic circuitry at least in part on processing of the output signal of the first circuitry by the programmable logic circuitry in accordance with communication protocol parameters that are programmed into the programmable logic circuitry.
6 more elements
Programmable logic circuitry comprising:
- hard IP circuitry including:
- (1) circuitry for making a number of successively received serial data bits available in parallel, all of the serial data bits being received via a single serial data signal selected from the group consisting of a differential input signal pair and a single-ended input signal,
- (2) circuitry for selecting aligned bytes of data from the parallel bits made available by the circuitry for making,
- (3) code-valid-checker circuitry for detecting whether an aligned byte selected by the circuitry for selecting corresponds to a valid byte code, and
- (4) CRD-error-checker circuitry for performing a current running disparity check on each aligned byte from the circuitry for selecting;
- and
- programmable logic circuitry for receiving (1) the aligned bytes from the circuitry for selecting, (2) an output signal of the code-valid-checker circuitry, and (3) an output signal of the CRD-error-checker circuitry, the programmable logic circuitry being configurable to (a) synchronize the aligned bytes in accordance with communication protocol parameters that are programmed into the programmable logic circuitry, including use of at least one of the output signal of the code-valid-checker circuitry and the output signal of the CRD-error-checker circuitry to determine when changing aligned byte selection of the circuitry for selecting is needed, and (b) feed back to the hard IP circuitry a signal for affecting operation of the circuitry for selecting when the programmable logic circuitry determines that changing aligned byte selection of the circuitry for selecting is needed.
4 more elements
Programmable logic circuitry comprising:
- hard IP circuitry including:
- (1) circuitry for making a number of successively received serial data bits available in parallel, all of the serial data bits being received via a single serial data signal selected from the group consisting of a differential input signal pair and a single-ended input signal,
- (2) circuitry for selecting, in parallel, two aligned bytes of data from the parallel bits made available by the circuitry for making,
- (3) code-valid-checker circuitry for detecting whether each of the aligned bytes selected by the circuitry for selecting corresponds to a valid byte code, and
- (4) CRD-error-checker circuitry for performing a current running disparity check on each of the aligned bytes from the circuitry for selecting;
- and
- programmable logic circuitry for receiving (1) the aligned bytes from the circuitry for selecting, (2) output signals of the code-valid-checker circuitry, and (3) output signals of the CRD-error-checker circuitry, the programmable logic circuitry being configurable to (a) synchronize the aligned bytes in accordance with communication protocol parameters that are programmed into the programmable logic circuitry, including use of the output signals of both the code-valid-checker circuitry and the CRD-error-checker circuitry to determine when changing aligned bytes selection of the circuitry for selecting is needed, and (b) feed back to the hard IP circuitry a signal for affecting operation of the circuitry for selecting when the programmable logic circuitry determines that changing aligned bytes selection of the circuitry for selecting is needed.
4 more elements
Dependencies are inferred from the claim text.