Customized silicon chips produced using dynamically configurable polymorphic network

A method for applying a desired interconnection scheme to a polymorphic network of a customizable semiconductor chip to provide a desired functionality for the customizable semiconductor chip, wherein the customizable semiconductor chip includes at least one functional component that is coupled to the polymorphic network in a semiconductor die, comprising the steps of:

• (a) providing configuration data that define the desired interconnection scheme specifying interconnections between ports on the at least one functional component;
• (b) loading the configuration data into memory registers that define the state of configurable data interconnections within the polymorphic network to achieve the desired interconnection scheme;
• and
• (c) while running an application on the customizable semiconductor chip that will employ the desired interconnection scheme, applying the configuration data stored in the memory to selectively modify signal conveyance resources of the polymorphic network to achieve specific interconnections between the ports of the at least one functional component.

A polymorphic network that is configured to interconnect ports and to enable redefining interconnections between the ports of one or more functional components, comprising:

• (a) a customizable semiconductor chip substrate that includes a plurality of ports adapted to electrically connect to corresponding ports on one or more functional components and including input connections adapted for coupling the customizable semiconductor chip substrate into an external circuit;
• (b) a plurality of configurable data connections that can be selectively set to open or close conductive paths between and through specific electrical conductors in the polymorphic network to customize interconnections between the ports on the one or more functional components;
• and
• (c) memory registers in which are stored connection data defining states of the configurable data connections to achieve a desired interconnection scheme for electrically interconnecting the plurality of ports of the polymorphic network, the states of the configurable data connections being modifiable at any time until an application that will use the polymorphic network is run.

A customizable semiconductor chip, comprising:

• (a) at least one functional electronic component, each functional electronic component having a plurality of first connection ports used for input and output of electrical signals;
• and
• (b) a polymorphic network comprising:
• (i) a semiconductor substrate on which the at least one functional electronic component is bonded;
• (ii) a plurality of second connection ports that are electrically connected to the first connection ports;
• (iii) a plurality of signal conveyance resources for selectively interconnecting specific ones of the second connection ports to specific other ones of the second connection ports in a desired interconnection scheme wherein the desired interconnection scheme can be modified up to a time that an application that will use the desired interconnection scheme is run by the customizable semiconductor chip;
• and
• (iv) a plurality of regions that are interconnected by selectively configurable crossbars, each region including a plurality of selectively configurable slices, wherein each selectively configurable slice includes:
• (1) an input queue;
• (2) a router that determines a route for data;
• (3) broadcast conductors for the route;
• (4) configurable data connections;
• and
• (5) an arbiter that controls data flow.

A method for applying a desired interconnection scheme to a polymorphic network of a customizable semiconductor chip to provide a desired functionality for the customizable semiconductor chip, wherein the customizable semiconductor chip includes at least one functional component that is coupled to the polymorphic network in a semiconductor die, comprising the steps of:

• (a) providing configuration data that define the desired interconnection scheme specifying interconnections between ports on the at least one functional component;
• (b) loading the configuration data into memory registers that define the state of configurable data interconnections within the polymorphic network to achieve the desired interconnection scheme;
• and
• (c) while running an application on the customizable semiconductor chip that will employ the desired interconnection scheme, automatically applying the configuration data stored in the memory to selectively modify signal conveyance resources of the polymorphic network to achieve specific interconnections between the ports of the at least one functional component, including the steps of:
• (i) selectively reconfiguring a plurality of crossbars interconnecting a plurality of regions comprising the polymorphic network;
• and
• (ii) selectively configuring interconnections between a plurality of slices comprising each of the plurality of regions, by interconnecting the plurality of slices with double crossbars, and enabling redefinition of input connections and output connections between slices with the double crossbars, in accord with the desired interconnection scheme.

A polymorphic network that is configured to interconnect ports and to enable redefining interconnections between the ports of one or more functional components, comprising:

• (a) a customizable semiconductor chip substrate that includes a plurality of ports adapted to electrically connect to corresponding ports on one or more functional components and including input connections adapted for coupling the customizable semiconductor chip substrate into an external circuit, wherein said customizable semiconductor chip substrate includes conductors that distribute electrical power to energize one or more functional components, and routes any required clocking signals to the one or more functional components;
• (b) a plurality of configurable data connections that can be selectively set to open or close conductive paths between and through specific electrical conductors in the polymorphic network;
• and
• (c) memory registers in which are stored connection data defining states of the configurable data connections to achieve a desired interconnection scheme for electrically interconnecting the plurality of ports of the polymorphic network, the states of the configurable data connections being modifiable at any time until an application that will use the polymorphic network is run.