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US 7,598,765 B2Granted
Redundant configuration memory systems and methods
AssigneeLattice Semiconductor Corporation
InventorsSatwant Singh, Chan-Chi Jason Cheng
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Abstract
Systems and methods are disclosed directed to techniques with respect to defective configuration memory cells. For example, in accordance with an embodiment of the present invention, a programmable logic device includes a plurality of configuration memory cells; and at least one spare memory cell, wherein the at least one spare memory cell is adapted to store configuration data to provide to at least one defective configuration memory cell.
Claims12
A programmable logic device comprising:
- a plurality of configuration memory cells;
- and
- at least one spare memory cell, wherein the at least one spare memory cell is adapted to store configuration data to provide to at least one defective configuration memory cell to maintain a stored value of the configuration data within the at least one defective configuration memory cell,
- the at least one spare memory cell including at least one driver to drive the configuration data stored in the at least one spare memory cell to the at least one defective configuration memory cell during a user mode of operation to maintain a proper configuration data value within the at least one defective configuration memory cell;
- a plurality of bitlines;
- a plurality of wordlines;
- a data shift register adapted to provide the configuration data to the plurality of configuration memory cells via the bitlines;
- and
- an address shift register adapted to provide programming signals to the plurality of configuration memory cells via the wordlines.
6 more elements
A programmable logic device comprising:
- a plurality of configuration memory cells;
- at least one spare memory cell, wherein the at least one spare memory cell is adapted to store configuration data to provide to at least one defective configuration memory cell to maintain a stored value of the configuration data within the at least one defective configuration memory cell;
- a plurality of bitlines;
- a plurality of wordlines;
- a data shift register adapted to provide the configuration data to the plurality of configuration memory cells via the bitlines;
- an address shift register adapted to provide programming signals to the plurality of configuration memory cells via the wordlines;
- and
- wherein during a user mode of operation the address shift register is adapted to provide, via at least one wordline, a programming signal to the at least one defective configuration memory cell, and wherein the data shift register is adapted to provide, via at least one of the bitlines, the configuration data from the at least one spare memory cell to the at least one defective configuration memory cell to maintain a proper configuration data value within the at least one defective configuration memory cell.
5 more elements
A programmable logic device comprising:
- a plurality of configuration memory cells;
- at least one spare memory cell, wherein the at least one spare memory cell is adapted to store configuration data to provide to at least one defective configuration memory cell to maintain a stored value of the configuration data within the at least one defective configuration memory cell;
- means for providing a programming signal to the at least one defective configuration memory cell during a user mode of operation;
- and
- means for providing the configuration data from the at least one spare memory cell to the at least one defective configuration memory cell to maintain a proper configuration data value within the at least one defective configuration memory cell during a user mode of operation;
- and
- non-volatile memory adapted to store in formation regarding the at least one defective configuration memory cell, wherein the information is used by the programming signal providing means;
- and
- wherein the plurality of configuration memory cells form sections, with each of the sections comprising at least one of the spare memory cells and at least one of the configuration data providing means.
6 more elements
A method comprising:
- providing a plurality of bitlines;
- providing a plurality of wordlines;
- providing a data shift register adapted to provide configuration data to a plurality of configuration memory cells via the bitlines;
- providing an address shift register adapted to provide programming signals to the plurality of configuration memory cells via the wordlines;
- storing the configuration data within the configuration memory cells of a programmable logic device;
- storing, within spare memory cells of the programmable logic device, the configuration data associated with certain ones of the configuration memory cells;
- and driving by the spare memory cells the configuration data to the certain ones of the configuration memory cells to maintain proper configuration data values stored within the certain ones of the configuration memory cells.
4 more elements
A method comprising:
- providing a plurality of bitlines;
- providing a plurality of wordlines;
- providing a data shift register adapted to provide configuration data to a plurality of configuration memory cells via the bitlines;
- providing an address shift register adapted to provide programming signals to the plurality of configuration memory cells via the wordlines;
- storing the configuration data within the configuration memory cells of a programmable logic device;
- storing, within spare memory cells of the programmable logic device, the configuration data associated with certain ones of the configuration memory cells;
- providing the configuration data from the spare memory cells to the certain ones of the configuration memory cells to maintain proper configuration data values stored within the certain ones of the configuration memory cells;
- and
- obtaining the configuration data stored in the certain ones of the configuration memory cells by reading back the configuration data stored in the spare memory cells.
6 more elements
Dependencies are inferred from the claim text.