Semiconductor integrated circuit having a degradation notice signal generation circuit
AssigneeKabushiki Kaisha Toshiba
InventorShinichi Yasuda
Life of this patent
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Abstract
It is made possible to detect degradation in a circuit before an operation fault will occur. A semiconductor integrated circuit includes: a circuit to be tested; a plurality of logical circuits which have different logical thresholds and which perform operation on an output of the circuit to be tested, on the basis of the logical thresholds; and a degradation notice signal generation circuit which generates a degradation notice signal to give notice that the circuit to be tested has degraded, when outputs of the logical circuits do not coincide with each other.
Claims20
A semiconductor integrated circuit comprising:
- a circuit to be tested;
- a plurality of logical circuits which have different logical thresholds and which perform operation on an output of the circuit to be tested, on the basis of the logical thresholds;
- and
- a degradation notice signal generation circuit which generates a degradation notice signal to give notice that the circuit to be tested has degraded, when outputs of the logical circuits do not coincide with each other.
A semiconductor integrated circuit comprising:
- a plurality of circuits to be tested which are same in configuration;
- a plurality of logical voltage variable circuits which are provided so as to be respectively associated with the circuits to be tested, each of which has a variable logical voltage threshold and performs operation on an output of the associated circuit to be tested, on the basis of the logical voltage threshold;
- and
- a plurality of degradation notice signal generation circuits which are provided so as to be respectively associated with the logical voltage variable circuits, and each of which generates a degradation notice signal to give notice that the associated circuit to be tested has degraded, provided that the output of the associated logical voltage variable circuit differs when the logical voltage threshold of the associated logical voltage variable circuit is changed.
A semiconductor integrated circuit comprising:
- a circuit to be tested having first and second partial circuits;
- a test line;
- a first switch provided between an output of the first partial circuit and the test line;
- a second switch provided between an output of the second partial circuit and the test line;
- a plurality of logical inversion circuits which are connected to the test line, which have different logical inversion thresholds, and each of which inverts an output of at least one of the first and second partial circuits sent via the test line according to states of the first and second switches, on the basis of the logical inversion threshold;
- and
- a degradation notice signal generation circuit which generates a degradation notice signal to give notice that the circuit to be tested has degraded, when outputs of the logical inversion circuits do not coincide.
Dependencies are inferred from the claim text.