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US 7,598,630 B2Granted
IC with on-die power-gating circuit
AssigneeIntel Corporation
InventorEdward Burton
Life of this patent
Estimating the term…
Abstract
In some embodiments a semiconductor device is described that includes, on a single die, both a functional circuit and a power-gating circuit. The power-gating circuit may be used to control the power delivered to core circuit elements on the semiconductor device. The power may be provided to and possibly from the power-gating circuit using underutilized die connection elements. Other embodiments are otherwise disclosed herein.
Claims30
A computer comprising
- an off-die memory device;
- a processor die, comprising:
- a plurality of die connection elements, wherein a first subset of the plurality of die connection elements receive power;
- a processor circuit;
- and
- a power-gating circuit electrically connected between the first subset of die connection elements and the processor circuit, wherein a second subset that is at least a portion of the first subset of die connection elements are not over the power-gating circuit, and wherein the power-gating circuit controls the application of power to the processor circuit by switchably interconnecting the first subset of the die connection elements to the processor circuit;
- and
- a substrate having
- an ungated conductive area to electrically connect a power supply input to an input of the power-gating circuit via the first subset of the die connection elements;
- and
- a gated conductive area electrically connected to an output of the power-gating circuit via a third subset of die connection elements and to the functional circuit via a fourth subset of die connection elements that are above the functional circuit, wherein a fifth subset that is at least a portion of the third subset of die connection elements are not over the power-gating circuit.
8 more elements
A semiconductor die, comprising:
- a plurality of die connection elements formed on the semiconductor die;
- a functional circuit including a plurality of devices formed in the semiconductor die and operating together to perform certain functions, wherein a portion of the functional circuit is formed above a first subset of the plurality of die connection elements that are not utilized to directly provide power or signals thereto;
- and
- a power-gating circuit formed in the semiconductor die and electrically connected between a power source and the functional circuit to control power provided to the functional circuit, wherein a connection between the power gating circuit and the power source is capable of handling peak current and peak current transitions associated with the functional circuit, and wherein the connection includes at least a second subset of the plurality of die connection elements and the second subset includes at least a portion of the first subset.
1 more element
A device, comprising:
- a substrate;
- a power supply input;
- a conductive area, on or in the substrate, electrically connected to the power supply input;
- and
- a semiconductor die coupled to the substrate, the die including:
- a semiconductor core including a plurality of devices formed in the semiconductor die and operating together to perform certain functions;
- and
- a power-gating circuit, electrically connected to the conductive area and the semiconductor core, to switchably provide power to the semiconductor core, wherein the power-gating circuit is electrically connected to the conductive area via die connection elements, wherein a first subset of the die connection elements are below the semiconductor core but are not utilized to directly provide power or signals thereto, and wherein the die connection elements are capable of handling peak current and peak current transitions associated with the semiconductor core.
5 more elements
A computer comprising:
- an off-die memory device;
- and
- a processor die, comprising:
- a plurality of die connection elements;
- a processor circuit;
- and
- a power-gating circuit electrically connected between a first subset of die connection elements and the processor circuit, wherein the first subset includes a second subset of die connection elements that are below the processor circuit and are not utilized to provide power or signals thereto, wherein the power-gating circuit controls the application of power to the processor circuit by switchably interconnecting the first subset of the die connection elements to the processor circuit, and wherein the first subset of the die connection elements are capable of handling peak current and peak current transitions associated with the processor circuit.
4 more elements
Dependencies are inferred from the claim text.