Silicided polysilicon spacer for enhanced contact area
AssigneesInternational Business Machines Corporation, Samsung Electronic Co., Ltd., Chartered Semiconductor Manufacturing Ltd.
InventorsThomas W. Dyer, Sunfei Fang, Ja-Hum Ku, Yong Meng Lee
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Abstract
An integrated circuit device having an increased source/drain contact area by a formed silicided polysilicon spacer. The polysilicon sidewall spacer is formed having a height less than seventy percent of said gate conductor height, and having a continuous surface silicide layer over the deep source and drain regions. The contact area is enhanced by the silicided polysilicon spacer.
Claims2
An integrated circuit device having increased source/drain contact area comprising:
- a transistor device having a gate conductor including conductive polysilicon sidewall spacers, said conductive polysilicon sidewall spacers having a reduced height of less than fifty percent of said gate conductor height;
- including a dielectric spacer between said gate conductor and said conductive polysilicon sidewall spacers, wherein said dielectric spacer is selected from nitride or a low dielectric constant material such as SiCOH;
- and
- having a continuous conductive surface silicide layer on said conductive polysilicon sidewall spacers having said reduced height and over deep source and drain regions to extend said source/drain contact area.
A method to increase source/drain contact area of an integrated circuit transistor which is applicable to a silicon substrate having isolation structures, said method comprising:
- forming a gate structure on said silicon substrate having a gate conductor, shallow trench isolation structures, and ion implantations comprising the steps;
- forming a pad oxide layer on said silicon substrate;
- forming a pad nitride layer on said pad oxide layer;
- patterning said nitride layer to form a shallow trench isolation structure;
- stripping said nitride layer using a hot phosphoric acid process;
- performing an ion implantation process for a well and a voltage threshold region of said gate structure, wherein said gate structure is subjected to rapid thermal annealing after said ion implantation;
- stripping said pad oxide;
- forming a gate dielectric;
- depositing a gate polysilicon layer;
- planarizing and patterning said gate polysilicon layer;
- etching said gate polysilicon layer to form said gate conductor;
- forming extension ion implants extending from said gate conductor;
- depositing an etch-stop oxide layer;
- forming nitride spacers adjacent said gate conductor sides;
- forming conductive polysilicon spacers along side of said nitride spacers and adjacent each side of said gate conductor sides;
- performing a source/drain ion implantation process;
- shortening said conductive polysilicon spacers by etching such that at least one of said conductive polysilicon spacers is at a height less than a height of said adjacent gate conductor, wherein said height of said at least one conductive polysilicon spacer is thirty percent, fifty percent, or seventy percent of said gate conductor height
- performing an oxide etch to remove said etch-stop oxide layer and expose said gate conductor and said source/drain ion implantation regions;
- performing a selective epitaxial silicon deposition;
- and
- forming a conductive silicide on said exposed gate conductor, on said shortened conductive polysilicon spacers and on said exposed source/drain ion implantation regions to extend said source/drain contact area.
Dependencies are inferred from the claim text.