Memory device and method for manufacturing the same

Abstract

A split gate (flash) EEPROM cell and a method for manufacturing the same is disclosed, in which a control gate and a floating gate are formed in a vertical structure, to minimize a size of the cell, to obtain a high coupling ratio, and to lower a programming voltage. The split gate EEPROM cell includes a semiconductor substrate having a trench; a tunneling oxide layer at sidewalls of the trench; a floating gate, a dielectric layer and a control gate in sequence on the tunneling oxide layer; a buffer dielectric layer at sidewalls of the floating gate and the control gate; a source junction in the semiconductor substrate at the bottom surface of the trench; a source electrode in the trench between opposing buffer dielectric layers, electrically connected to the source junction; and a drain junction on the surface of the semiconductor substrate outside the trench.

Dependencies are inferred from the claim text.