Hybrid carbon nanotude FET(CNFET)-FET static RAM (SRAM) and method of making same

#1. Technical Field

#This invention relates in to a field effect device having a channel of carbon nanofabric, a static random access memory (SRAM) made of such, and a method of making the same.

#2. Discussion of Related Art

#In the Drawing,

#FIG. 1 illustrates a schematic of a prior art device;

#FIGS. 2A and 2B illustrate schematic drawings of memory cells according to aspects of the invention;

#Stackable, scalable, low leakage SRAM cell load devices are needed for new SRAM generations. Carbon nanotube FET (CNFET) transistors, more specifically, P-Type CNFET transistors (P-CNFETs) make excellent stackable load devices. P-CNFETs do not require a silicon substrate, are scalable, and have very low leakage currents. Research has demonstrated that a single (one) SWNT fiber spanning the distance between source and drain device regions exhibits 10× greater mobility than a PFET device, is scalable to sub-20 nm source-to-drain channel lengths, and has low OFF state leakage current. See Durkorp et al., “Extraordinary Mobility in Semiconducting Carbon Nanotubes,” Nano Lett. 2004, Vol. 4 No. 135-39. In spite of high single SWNT fiber current density carrying capability, replacing PFET load devices requires multiple SWNTs spanning the distance between source and drain regions to carry the total ON state load current. Also, these multiple SWNT P-CNFET devices must be made compatible and integrated with CMOS technology used in SRAM fabrication. This includes multiple SWNT deposition, patterning at desired locations, and interconnecting with NFET devices in the SRAM cell. Since SWNTs may be semiconducting or metallic, under certain embodiments metallic SWNTs in the P-CNFET channel region spanning the distance between source and drain must be burned-off. Finally, the electrical characteristics of the CNFET devices must be optimized for operation in the voltage range required for product design.

#Preferred embodiments of the present invention provide fabrication solutions and corresponding structures for the controlled placement, patterning, and integration of stacked P-CNFET devices with CMOS technology to enable the design of scalable, dense, high performance and very low power hybrid CNFET-FET SRAM memory products. Preferred embodiments of the present invention provide P-CNFETs with multiple SWNTs spanning the distance between source and drain to form the channel region of the P-CNFETs. Preferred embodiments of the present invention optimize the electrical characteristics of these P-CNFETs for high performance and low leakage. Preferred embodiments of the present invention provide a means of burning-off metallic SWNTs in the P-CNFET channel region such that only semiconducting SWNTs spanning the region between source and drain remain in the channel region. Preferred embodiments of the present invention optimize the electrical characteristics of the combined P-CNFET and FET devices and ensure operation in the voltage range required SRAM memory products, both stand alone and embedded.

#Overview of SRAM Memory Cells