US 7,598,538 B2 · ESD protecting circuit and manufacturing method thereof

Abstract

An ESP protecting circuit and a manufacturing method thereof are provided. The ESP protecting circuit includes a device isolation layer, first and second high-concentration impurity regions, a third high-concentration impurity region of a complementary type, first and second conductive wells, and a fourth conductive impurity region. The ESD protecting circuit is configured as a field transistor without a gate electrode, and the high breakdown voltage characteristics of the field transistor are lowered by implanting impurity ions, providing an ESD protecting circuit with a low breakdown voltage and low leakage current. Because the leakage current is reduced, the ESD protecting circuit can be used for an analog I/O device that is sensitive to current fluxes. Also, an N-type well may protect a junction of the field transistor.

Drawings

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Drawings

Claims20

Dependent claims

An ESD (electro-static discharge) protecting circuit comprising:

a device isolation layer in a field region of a semiconductor substrate having a first conductivity type;
first and second high-concentration impurity regions in the semiconductor substrate, isolated from each other by the device isolation layer and having a second conductivity type, wherein the first high-concentration impurity region contacts a first sidewall surface of the device isolation layer and the second high-concentration impurity region contacts a second sidewall surface of the device isolation layer opposite to said first sidewall surface;
a third high-concentration impurity region in the semiconductor substrate, isolated from the second high-concentration impurity region by the device isolation layer, and having the first conductivity type;
a first well in a first portion of the semiconductor substrate in contact with and below the second and third high-concentration impurity regions and below a first portion of the first high-concentration impurity region, and having the first conductivity type
a second well in a second portion of the semiconductor substrate in contact with and below a second portion of the first high-concentration impurity region on one side of the first well, and having the second conductivity type;
and
a fourth impurity region below the first high-concentration impurity region at a boundary between the first and second wells, the fourth impurity region separating the first high-concentration impurity region from the first well, and having the first conductivity type.

4 more elements

Dependencies are inferred from the claim text.

Description3,508 words

Summary1,360 words

#1. Field of the Invention

#The present invention relates to an electro-static discharge (ESD) circuit, and more particularly, to an ESD protecting circuit and a manufacturing method thereof capable of protecting a junction of a field transistor, and suitable for an analog input/output device by giving the device a low breakdown voltage.

#2. Description of the Related Art

Brief description of the drawings3 figures

#The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the principle of the invention. In the drawings:

#FIG. 1 is a sectional view of an ESP protecting circuit according to the related art;

#FIG. 2 is a sectional view of an ESD protecting circuit according to the present invention; and

Detailed description2,048 words

#Reference will now be made in detail to an ESD protecting circuit and a manufacturing method thereof, according to preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts.

#FIG. 2 is a sectional view of an ESD protecting circuit according to the present invention.

#An ESD protecting circuit according to the present invention, as described above, includes an N-type well in a field transistor structure that does not require a gate electrode and adds an ion implant process step to reduce leakage voltage, protect a junction, and give the field transistor a low breakdown voltage, so that it is appropriate for an analog I/O device.

Facts

Application

11/502,834Filed 11 Aug 2006

Priority

KR 10-2005-007376611 Aug 2005

Published

US 2007/0034897 A115 Feb 2007

Granted

6 Oct 2009

Term ended

19 Aug 2026

Estimated · how

20 years from earliest known nonprovisional domestic filing plus recorded patent term adjustment, including 8 days of adjustment. Maintenance-fee lapses, terminal disclaimers and statutory extensions have not been checked. The continuity chain may be incomplete; this is not an enforceability determination.

Classification6 codes

H10D 89/711
For devices having insulated gate electrodes, e.g. for IGFETs or IGBTs: using bipolar transistors as protective elements
H10D 8/041
Manufacture or treatment: of multilayer diodes
H10D 8/80
Diodes: pNPN diodes, e.g. Shockley diodes or break-over diodes
H10D 62/108
By having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination…

Timeline

11 Aug 2005Priority claimedKR 10-2005-0073766
11 Aug 2006Application filedUS 11/502,834
11 Aug 2006Assigned to Dongbu Electronics Co., Ltd.assignment of assignor's interest
15 Feb 2007PublishedUS 2007/0034897 A1
6 Oct 2009GrantedUS 7,598,538 B2
29 Nov 2017Assigned to Dongbu Hitek Co., Ltd.merger and change of name
30 Nov 2017Assigned to Db Hitek Co., Ltdchange of name
19 Aug 2026Term endedEstimated, includes 8 days of adjustment

ESD protecting circuit and manufacturing method thereof

Life of this patent

ESD protecting circuit and manufacturing method thereof

Life of this patent

Life of this patent

Abstract

Drawings

Drawings

Claims20

Description3,508 words

Drawings

Classification6 codes

Life of this patent

Description3,508 words