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US 7,598,516 B2Granted
Self-aligned process for nanotube/nanowire FETs
AssigneeInternational Business Machines Corporation
InventorsPhaedon Avouris, Roy A. Carruthers, Jia Chen, Christophe G. M. M. Detavernier, Christian Lavoie, Hon-Sum Philip Wong
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Abstract
A complementary metal oxide semiconductor (CMOS) device, e.g., a field effect transistor (FET), that includes at least one one-dimensional nanostructure that is typically a carbon-based nanomaterial, as the device channel, and a metal carbide contact that is self-aligned with the gate region of the device is described. The present invention also provides a method of fabricating such a CMOS device.
Claims15
A semiconductor structure comprising:
- a substrate comprising at least one gate region located thereon, said at least one gate region comprising a layer of at least one one-dimensional nanostructure, a gate dielectric located on a surface of said at least one one-dimensional nanostructure and a gate electrode located on a surface of said gate dielectric, where said layer of at least one one-dimensional nanostructure is interposed between said substrate and said gate electrode;
- at least one spacer located on a surface of said layer of at least one one-dimensional nanostructure, wherein an inner edge of said at least one spacer is laterally abutting both a sidewall of said gate electrode and a sidewall of said gate dielectric;
- and
- a metal carbide contact located on a surface of said substrate, wherein said metal carbide contact is aligned to and laterally abuts, but does not overlap, both a sidewall edge of said layer of at least one one-dimensional nanostructure and a sidewall edge of said at least one spacer.
1 more element
A semiconductor structure comprising:
- a substrate comprising at least one gate region located thereon, said at least one gate region comprising a layer of at least one one-dimensional nanostructure, a gate dielectric located on a surface of said at least one one-dimensional nano structure and a gate electrode located on a surface of said gate dielectric, where said layer of at least one one-dimensional nanostructure is interposed between said substrate and said gate electrode;
- at least one spacer located on a surface of said layer of at least one one-dimensional nano structure, wherein an inner edge of said at least one spacer is laterally abutting both a sidewall of said gate electrode and a sidewall of said gate dielectric;
- and
- a metal carbide contact located on a surface of said substrate, wherein said metal carbide contact is aligned to and laterally abuts, but does not overlap, both a sidewall edge of said layer of at least one one-dimensional nanostructure and a sidewall edge of said at least one spacer, wherein said sidewall of said gate electrode and said sidewall of said gate dielectric are vertically coincident and aligned to each other.
1 more element
A semiconductor structure comprising:
- a substrate comprising at least one gate region located thereon, said at least one gate region comprising a layer of at least one one-dimensional nanostructure, a gate dielectric located on a surface of said at least one one-dimensional nanostructure and a gate electrode located on a surface of said gate dielectric, where said layer of at least one one-dimensional nanostructure is interposed between said substrate and said gate electrode;
- at least one spacer located on a surface of said layer of at least one one-dimensional nanostructure, wherein an inner edge of said at least one spacer is laterally abutting both a sidewall of said gate electrode and a sidewall of said gate dielectric;
- and
- a metal carbide contact located on a surface of said substrate, wherein said metal carbide contact is aligned to and laterally abuts, but does not overlap, both a sidewall edge of said layer of at least one one-dimensional nanostructure and a sidewall edge of said at least one spacer, and wherein said at least one spacer does not overlap said metal carbide contact.
1 more element
Dependencies are inferred from the claim text.