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US 7,598,165 B2Granted
Methods for forming a multiplexer of a memory device
AssigneeMicron Technology, Inc.
InventorSeiichi Aritome
Life of this patent
Estimating the term…
Abstract
A method of forming a portion of a multiplexer of a memory device includes forming a plurality of conductive plugs on a semiconductor substrate and forming first and second bit lines overlying the conductive plugs so that a pair of successively adjacent first and second bit lines is in contact with the same conductive plug.
Claims44
A method of forming a portion of a multiplexer of a memory device, comprising:
- forming a plurality of conductive plugs on a semiconductor substrate;
- and
- forming pairs of successively adjacent first and second bit lines overlying the conductive plugs so that the first and second bit lines of a pair of successively adjacent first and second bit lines are both in contact with the same conductive plug;
- and
- respectively coupling the first and second bit lines of each pair of successively adjacent first and second bit lines to first and second multiplexer gates.
2 more elements
A method of forming a portion of a multiplexer of a memory device, comprising:
- forming a plurality of conductive plugs on a semiconductor substrate;
- and
- forming pairs of successively adjacent first and second bit lines overlying the conductive plugs so that the first and second bit lines of a pair of successively adjacent first and second bit lines are both in contact with the same conductive plug;
- wherein the first bit lines terminate within the multiplexer and the second bit lines extend exteriorly of the multiplexer;
- wherein a spacer loops around an end of each of the first bit lines;
- and
- wherein the spacer overlies the conductive plugs.
4 more elements
A method of forming a portion of a multiplexer of a memory device, comprising:
- forming a plurality of conductive plugs on a semiconductor substrate;
- and
- forming pairs of successively adjacent first and second bit lines overlying the conductive plugs so that the first and second bit lines of a pair of successively adjacent first and second bit lines are both in contact with the same conductive plug;
- and
- forming a pair of successively adjacent third and fourth bit lines between successive pairs of successively adjacent first and second bit lines, the third and fourth bit lines overlying and in contact with an etch-stop layer that overlies the conductive plugs.
2 more elements
A method of forming a portion of a multiplexer of a memory device, comprising:
- forming a plurality of first conductive plugs on a semiconductor substrate;
- forming a first insulation layer overlying the plurality of first conductive plugs;
- forming an etch-stop layer overlying the first insulation layer;
- removing portions of the etch-stop layer to expose portions of the first insulation layer;
- forming a second insulation layer overlying the etch-stop layer and the exposed portions of the first insulation layer;
- forming first and second bit lines through the first and second insulation layers so that a pair of successively adjacent first and second bit lines are both in contact with a first conductive plug;
- and
- forming pairs of successively adjacent third and fourth bit lines through the second insulation material so that the pairs of successively adjacent third and fourth bit lines are in contact with the etch stop layer at locations adjacent the first conductive plugs;
- wherein a pair of successively adjacent third and fourth bit lines are located between successive pairs of successively adjacent first and second bit lines.
6 more elements
A method of forming a portion of a multiplexer of a memory device, comprising:
- forming a first insulation layer on a semiconductor substrate;
- forming a plurality of holes through the first insulation layer that expose the semiconductor substrate;
- forming a conductive plug in each of the holes in contact with the semiconductor substrate;
- forming a second insulation layer overlying the conductive plugs;
- forming an etch-stop layer on the second insulation layer;
- removing portions of the etch-stop layer to expose portions of the second insulation layer;
- forming a third insulation layer overlying the etch-stop layer and the exposed portions of the second insulation layer;
- forming pairs of successively adjacent first and second trenches through the second and third insulation layers so that a pair of successively adjacent first and trenches exposes portions of each conductive plug;
- forming a pair of successively adjacent third and fourth trenches through the third insulation layer between successive pairs of successively adjacent pairs first and second trenches to expose portions of the etch stop layer;
- respectively forming first and second bit lines in the first and second trenches so that a pair of successively adjacent first and second bit lines is contact with each of the conductive plugs;
- and
- respectively forming third and fourth bit lines in the third and fourth trenches so that the third and fourth bit lines are in contact with the etch stop layer and so that a pair of successively adjacent third and fourth bit lines is formed between successive pairs of successively adjacent first and second bit lines.
9 more elements
A method of forming a portion of a multiplexer of a memory device, comprising:
- forming a first insulation layer on a semiconductor substrate;
- patterning the first insulation layer for exposing portions of the first insulation layer for removal;
- removing the exposed portions of the first insulation layer to form a plurality of holes through the first insulation layer that expose the semiconductor substrate;
- forming a conductive plug in each of the holes in contact with the semiconductor substrate;
- forming a second insulation layer overlying the conductive plugs;
- forming an etch-stop layer on the second insulation layer;
- patterning the etch-stop layer for exposing portions of the etch-stop layer for removal;
- removing the exposed portions of the etch-stop layer to expose portions of the second insulation layer;
- forming a third insulation layer overlying the etch-stop layer and the exposed portions of the second insulation layer;
- forming a plurality of mask segments on the third insulation layer;
- forming a dielectric layer overlying the mask segments and the third insulation layer;
- anisotropically removing portions of the dielectric layer such that remaining portions of the dielectric layer self align with and are disposed on sidewalls and an end wall of each the mask segments;
- removing the mask segments, leaving the spacers, wherein the spacers form a pattern for respectively exposing portions of the third insulation layer for removal;
- removing the exposed portions of the third insulation layer to form pairs of successively adjacent first and second trenches through the third insulation layer to expose portions of the second insulation layer, and forming a pair of successively adjacent third and fourth trenches through the third insulation layer between successive pairs of successively adjacent pairs first and second trenches to expose portions of the etch stop layer;
- removing the exposed portions of the second insulation layer, thereby extending the pairs of successively adjacent first and second trenches so that a pair of successively adjacent first and trenches exposes portions of each conductive plug;
- respectively forming first and second bit lines in the first and second trenches so that a pair of successively adjacent first and second bit lines is contact with each of the conductive plugs;
- and
- respectively forming third and fourth bit lines in the third and fourth trenches so that the third and fourth bit lines are in contact with the etch stop layer and so that a pair of successively adjacent third and fourth bit lines is formed between successive pairs of successively adjacent first and second bit lines.
15 more elements
Dependencies are inferred from the claim text.