Semiconductor device fabrication method

#This application is based upon and claims benefit of priority under 35 USC §119 from the Japanese Patent Application No. 2005-33351, filed on Feb. 9, 2005, the entire contents of which are incorporated herein by reference.

#The present invention relates to a semiconductor device fabrication method.

#Recently, to increase the degree of integration and the operating speed and reduce the power consumption and the fabrication cost, micropatterning of LSIs has advanced so that the minimum processing dimension (e.g., the gate length of a transistor) is nearly 0.1 μm. This LSI micropatterning is expected to advance in the future until the minimum processing dimension becomes 0.1 μm or less. For example, logic devices in which the gate length of a transistor is decreased to about 30 nm are developed.

#FIG. 1 is a longitudinal sectional view showing an element sectional structure in a predetermined step of a semiconductor device fabrication method according to the first embodiment of the present invention;

#FIG. 2 is a longitudinal sectional view showing an element sectional structure in a predetermined step of the same semiconductor device fabrication method;

#FIG. 3 is a longitudinal sectional view showing an element sectional structure in a predetermined step of the same semiconductor device fabrication method;

#Embodiments of the present invention will be described below with reference to the accompanying drawings.

#FIGS. 1 to 3 show an element isolation insulating film formation method according to the first embodiment of the present invention. As shown in FIG. 1, a silicon oxide (SiO2) film 20 about 5 nm thick is formed on a semiconductor substrate 10 by thermal oxidation, and a silicon nitride (SiN) film 30 about 150 nm thick which serves as a stopper of polishing by CMP to be performed later is formed by CVD.

#A silicon oxide (SiO2) film (not shown) is formed on the entire surface of the silicon nitride (SiN) film 30 by CVD. This silicon oxide (SiO2) film is coated with a photoresist (not shown), and exposure and development are performed to form a resist mask (not shown).