Method for forming inter-poly dielectric in shielded gate field effect transistor

#The invention relates in general to semiconductor power field effect transistors (FETs), and more particularly to a structure and method for forming an improved inter-poly dielectric (IPD) in a shielded gate FET.

#Shielded gate trench FETs are advantageous in that the shield electrode reduces the gate-drain capacitance (Cgd) and improves the breakdown voltage of the transistor. FIG. 1 is a simplified cross section view of a conventional shielded gate trench MOSFET. Trench 110 includes a shield electrode 114 directly below a gate electrode 122. Shield electrode 114 is insulated from adjacent silicon regions by a shield dielectric 112 which is generally thicker than gate dielectric 120. The gate and shield electrodes are insulated from one another by a dielectric layer 116 commonly referred to as inter-poly dielectric or IPD. The IPD layer must be of sufficient quality and thickness to support the required voltage between the gate and shield electrodes.

#The conventional shielded gate FET of FIG. 1 suffers from a number of drawbacks. First, gate electrode 122 has sharp bottom comers which together with the flat top surface of shield electrode 114 leads to high electric fields in these regions. Second, conventional methods for forming the IPD typically introduce an oxide layer on the mesas between trenches that must be removed at some point after the gate electrode has been formed. In removing this oxide some etching of the gate oxide down the trench sidewalls inevitably occurs, which may result in gate shorts and gate leakage. Other known techniques tie formation of the IPD to formation of the gate dielectric and thus the IPD thickness is limited to a set multiple of the gate dielectric thickness. This does not allow independent optimization of the gate dielectric and the IPD. The largest differential in thickness between the IPD and the gate dielectric achieved has been about three to one (i.e., for a given target gate dielectric thickness, the largest IPD thickness that has been achieved is about three times greater than that of the target gate dielectric thickness).

#FIG. 1 is a simplified cross section view of a conventional shielded gate trench MOSFET; and

#FIGS. 2A-2L are simplified cross section views at various stages of an exemplary process sequence for forming a shielded gate trench FET with improved inter-poly dielectric and gate dielectric, in accordance with an embodiment of the invention.

#In accordance with the present invention, an IPD layer of a shielded gate FET is formed by performing a thermal oxidation followed by deposition of a conformal layer of dielectric. A gate dielectric is then formed, followed by formation of the gate electrode. This method decouples the process for forming the IPD layer from that for forming the gate dielectric, enabling each of these dielectric layers to be independently optimized. A high quality, thick IPD can thus be formed to support the required voltage between the gate and shield electrodes without compromising the gate dielectric quality or thickness. Further, the conformal layer of dielectric helps obtain a smooth concave profile (i.e., like the inside of a bowl) along the top surface of the IPD which in turn results in a smooth bottom profile for the gate electrode. This helps reduce the electric field as compared to the conventional FET structure in FIG. 1 where the gate electrode has sharp lower corners.

#FIGS. 2A-2L are simplified cross section views at various stages of an exemplary process sequence for forming a shielded gate trench FET with improved IPD and gate dielectric, in accordance with an embodiment of the invention. In FIG. 2A, a trench 202 is formed in silicon region 204 using conventional masking and silicon etch techniques. In one embodiment, silicon region 204 comprises a relatively lightly doped n-type epitaxial layer extending over a highly conductive n-type substrate. In this embodiment, depending on the design goals, the trench can be etched to terminate within the epitaxial layer or extend deeper to terminate within the substrate. In FIG. 2B, a shield dielectric layer 206 (e.g., comprising oxide) lining the trench sidewalls and bottom as well as the surface of the mesa regions adjacent the trench is formed using known techniques. In one embodiment, the shield oxide is formed using high temperature (e.g., 1,150° C.) dry oxidation. The high temperature helps round out the trench bottom corners and form about 1,250 Å of shield oxide sufficient to support device breakdown.

#In FIG. 2C, a layer of polysilicon is deposited to fill the trench using conventional polysilicon deposition techniques. The deposited polysilicon is then recessed into the trench to thereby form shield electrode 208. The exposed portions of the shield dielectric layer are then thinned down, to for example 650 Å. In an embodiment where the shield electrode comprises oxide, a wet buffered oxide etch is used to thin down the shield oxide. The remaining exposed portion 206a of the shield dielectric helps prevent excessive growth of oxide along the trench sidewalls and mesa surfaces in the subsequent thermal oxidation step, and helps control the profile of the trenched cavity. Excessive growth of thermal oxide can lead to formation of voids in the subsequent deposited conformal dielectric. In one embodiment, the exposed portions of shield dielectric 206 are completely removed or alternatively the entire shield dielectric 206 is left intact.