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US 7,598,134 B2Granted
Memory device forming methods
AssigneeMicron Technology, Inc.
InventorChandra Mouli
Life of this patent
Estimating the term…
Abstract
A memory device includes an array of memory cells and peripheral devices. At least some of the individual memory cells include carbonated portions that contain SiC. At least some of the peripheral devices do not include any carbonated portions. A transistor includes a first source/drain, a second source/drain, a channel including a carbonated portion of a semiconductive substrate that contains SiC between the first and second sources/drains and a gate operationally associated with opposing sides of the channel.
Claims18
A memory device forming method comprising:
- providing a semiconductive substrate;
- forming a SiC layer in contact with a memory array region and a peripheral device region of the semiconductive substrate;
- removing the SiC layer from over the peripheral device region and leaving the SiC layer on at least a portion of the memory array region, a remainder of the SiC layer forming carbonated portions of the semiconductive substrate that contain SiC;
- forming an array of memory cells over the substrate, at least some of the individual memory cells including the carbonated portions;
- and
- forming peripheral devices including memory cell addressing circuitry and memory cell read circuitry over the substrate, at least some of the peripheral devices not including the carbonated portions.
3 more elements
A memory device forming method comprising:
- providing a semiconductive substrate;
- forming carbonated portions of the semiconductive substrate that contain SiC;
- forming an array of memory cells over the substrate, at least some of the individual memory cells including the carbonated portions and formation of such individual memory cells including forming a vertical transistor to include:
- a first source/drain;
- a second source/drain;
- a channel containing one of the carbonated portions between the first and second sources/drains with the channel elevationally above the first source/drain and the second source/drain elevationally above the channel;
- and
- a gate operationally associated with opposing sides of the channel;
- and
- forming peripheral devices including memory cell addressing circuitry and memory cell read circuitry over the substrate, at least some of the peripheral devices not including the carbonated portions.
7 more elements
A memory device forming method comprising:
- providing a semiconductive substrate;
- forming carbonated portions of the semiconductive substrate that contain SiC;
- forming an array of memory cells over the substrate, at least some of the individual memory cells including the carbonated portions and formation of such individual memory cells including forming a transistor to include;
- a first source/drain;
- a second source/drain;
- a gate recessed into the semiconductive substrate between the first and second sources/drains;
- and
- a channel containing one of the carbonated portions operationally associated with opposing sides of the gate;
- and
- forming peripheral devices including memory cell addressing circuitry and memory cell read circuitry over the substrate, at least some of the peripheral devices not including the carbonated portions.
7 more elements
A memory device forming method comprising:
- providing a semiconductive substrate;
- forming carbonated portions of the semiconductive substrate that contain SiC;
- forming an array of memory cells over the substrate, at least some of the individual memory cells including the carbonated portions and being formed by;
- forming a first transistor source/drain region in the semiconductive substrate;
- forming a second transistor source/drain region in the semiconductive substrate;
- forming a transistor channel that does not contain SiC between the first and second source/drain regions;
- and
- forming a storage node junction on the first source/drain region and a digit node junction on the second source/drain region, the storage node junction and/or digit node junction including one of the carbonated portions and being formed on epitaxial silicon of the respective source/drain region, the epitaxial silicon being elevationally above the channel;
- and
- forming peripheral devices including memory cell addressing circuitry and memory cell read circuitry over the substrate, at least some of the peripheral devices not including the carbonated portions.
7 more elements
Dependencies are inferred from the claim text.