US 7,598,112 B2 · Phase change memory devices and their methods of fabrication

Abstract

In an embodiment, a phase change memory device includes a semiconductor substrate of a first conductivity type and a first interlayer insulating layer disposed on the semiconductor substrate. A hole penetrates the first interlayer insulating layer. A first and a second semiconductor pattern are sequentially stacked in a lower region of the hole. A cell electrode is provided on the second semiconductor pattern. The cell electrode has a lower surface than a top surface of the first interlayer insulating layer. A confined phase change material pattern fills the hole on the cell electrode. An upper electrode is disposed on the phase change material pattern. The phase change material pattern in the hole is self-aligned with the first and second semiconductor patterns by the hole. A method of fabricating the phase change memory device is also provided.

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Claims12

Dependent claims

A method of fabricating a phase change memory device, comprising:

preparing a semiconductor substrate of a first conductivity type;
forming a first interlayer insulating layer on the semiconductor substrate;
patterning the first interlayer insulating layer to form a plurality of diode holes in the first interlayer insulating layer;
forming first semiconductor Patterns in lower regions of the diode holes;
forming second semiconductor patterns on the first semiconductor patterns;
forming cell electrodes on the second semiconductor patterns;
forming insulating contact spacers in the diode holes, wherein the insulating contact spacers are formed on sidewalls of the diode holes and on the cell electrodes;
forming lower electrodes in the diode holes, wherein the lower electrodes are formed on the insulating contact spacers and on the cell electrodes and wherein top surfaces of the lower electrodes are lower than a top surface of the first interlayer insulating layer and higher than a bottom surface of the first interlayer insulating layer;
forming phase change material patterns filling the diode holes, wherein the phase change material patterns are formed on the cell electrodes and on the insulating contact spacers, wherein the phase change material patterns extend over the top surface of the first interlayer insulating layer;
and
forming upper electrodes on the phase change material pattern,
wherein the first semiconductor patterns are formed to have the first conductivity type or a second conductivity type different from the first conductivity type, and the second semiconductor patterns are formed to have the first conductivity type,
wherein forming the first and second semiconductor patterns comprises:
forming recessed semiconductor patterns filling lower regions in the diode holes;
doping lower regions of the recessed semiconductor patterns with impurities of the first conductivity type or impurities of the second conductivity type;
and
doping upper regions of the recessed semiconductor patterns with impurities of the first conductivity type, and
wherein forming the recessed semiconductor patterns comprises:
forming a single crystalline semiconductor layer filling the diode holes using a selective epitaxial growth technique;
planarizing the single crystalline semiconductor layer to form single crystalline semiconductor patterns with flat top surfaces having the same level as a top surface of the first interlayer insulating layer;
and
after forming the single crystalline semiconductor patterns, partially etching the single crystalline semiconductor patterns to recess the single crystalline semiconductor patterns.

19 more elements

Dependencies are inferred from the claim text.

Description5,403 words

Summary1,696 words

#This application claims priority from Korean Patent Application No. 10-2005-0032898, filed Apr. 20, 2005, the disclosure of which is hereby incorporated by reference herein in its entirety.

#The present invention relates to semiconductor memory devices and their methods of fabrication, and, more particularly, to phase change memory devices having cell diodes and their methods of fabrication.

#Nonvolatile memory devices retain their stored data even when their power supplies are turned off. Thus, nonvolatile memory devices have been widely used in conjunction with computers, mobile telecommunication systems, memory cards and so on. For example, one widely used type of nonvolatile memory device is the flash memory device. Many flash memory devices employ memory cells having a stacked gate structure. The stacked gate structure of a flash memory device typically includes a tunnel oxide layer, a floating gate, an inter-gate dielectric layer, and a control gate electrode, which are sequentially stacked on a channel region.

Brief description of the drawings3 figures

#The features and advantages of the invention will be apparent from the descriptions of exemplary embodiments of the invention, as illustrated in the accompanying drawings. The drawings are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the invention.

#FIG. 1 is a plan view illustrating a portion of a cell array region of a phase change memory device according to an exemplary embodiment of the present invention.

#FIGS. 2A, 3A, 4A, 5A, 6A and 7A are cross-sectional views taken along line I-I′ of FIG. 1 to illustrate phase change memory devices according to an exemplary embodiment of the present invention and methods of their fabrication.

Detailed description3,559 words

#The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments of the invention are shown. This invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure is thorough and complete and fully conveys the scope of the invention to those skilled in the art. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. The same reference numerals are used to denote the same elements.

#FIG. 1 is a plan view illustrating a portion of a cell array region of a phase change memory device according to an exemplary embodiment of the present invention. Also, FIGS. 2A, 3A, 4A, 5A, 6A and 7A are cross-sectional views taken along line I-I′ of FIG. 1, and FIGS. 2B, 3B, 4B, 5B, 6B and 7B are cross-sectional views taken along line II-II′ of FIG. 1.

#First, phase change memory devices according to an exemplary embodiment of the present invention will be described with reference to FIGS. 1, 7A and 7B.

Facts

Application

11/392,310Filed 28 Mar 2006

Priority

KR 10-2005-003289820 Apr 2005

Published

US 2006/0237756 A126 Oct 2006

Granted

6 Oct 2009

Term ended

13 Aug 2026

Estimated · how

20 years from earliest known nonprovisional domestic filing plus recorded patent term adjustment, including 138 days of adjustment. Maintenance-fee lapses, terminal disclaimers and statutory extensions have not been checked. The continuity chain may be incomplete; this is not an enforceability determination.

Classification9 codes

H10N 70/8828
Compounds of sulfur, selenium or tellurium, e.g. chalcogenides: tellurides, e.g. GeSbTe
H10B 63/20
Resistance change memory devices, e.g. resistive RAM [ReRAM] devices: comprising selection components having two electrodes, e.g. diodes
H10B 63/80
Resistance change memory devices, e.g. resistive RAM [ReRAM] devices: arrangements comprising multiple bistable or multi-stable switching…
H10N 70/061
Manufacture or treatment of multistable switching devices: shaping switching materials

Timeline

20 Apr 2005Priority claimedKR 10-2005-0032898
28 Mar 2006Application filedUS 11/392,310
21 Jun 2006Assigned to Samsung Electronics Co., Ltd.assignment of assignor's interest
26 Oct 2006PublishedUS 2006/0237756 A1
6 Oct 2009GrantedUS 7,598,112 B2
13 Aug 2026Term endedEstimated, includes 138 days of adjustment

Phase change memory devices and their methods of fabrication

Life of this patent

Phase change memory devices and their methods of fabrication

Life of this patent

Life of this patent

Abstract

Drawings

Drawings

Claims12

Description5,403 words

Drawings

Classification9 codes

Life of this patent

Description5,403 words