Multi-stage charge pump without threshold drop with frequency modulation between embedded mode operations

An integrated circuit device, comprising:

• a memory having a first mode for at least one of programming and erasing and a second mode for reading;
• charge pump circuitry coupled to a node in the memory, operable in the first mode and the second mode, the charge pump circuitry including a plurality of charge pump stages, responsive to a plurality of clock signals;
• enable circuitry to enable all the charge pump stages in the plurality of charge pump stages in the first mode, and to enable less than all but at least one of the charge pump stages in the plurality of charge pump stages in the second mode
• wherein the enable circuitry includes a plurality of precharge circuits coupled to respective charge pump stages in the plurality of charge pump stages, at least one precharge circuit in the plurality of precharge circuits having a first state allowing a node on the corresponding charge pump stage to fluctuate at a level above the supply potential, and a second state coupling the node to a supply potential without inducing voltage loss of a threshold voltage drop, and thereby decoupling the corresponding stage from preceding stages in the plurality of stages;
• and
• a clock source including a plurality of clock generators, the clock source providing the plurality of clock signals;
• wherein the clock source includes a clock circuit including components tending to cause the frequency of the plurality of clock signals to change according to a first function, where the first function has an inverse relation with change in supply potential and is relatively unresponsive to changes in temperature
• circuitry providing control signals to said at least one precharge circuit and to the clock source, so that in the first mode the at least one precharge circuit is in the first state, and in the second mode the at least one precharge circuit is in the second state.

An integrated circuit device, comprising:

• a memory having a first mode for at least one of programming and erasing and a second mode for reading;
• charge pump circuitry coupled to a node in the memory, operable in the first mode and the second mode, the charge pump circuitry including a plurality of charge pump stages, responsive to a plurality of clock signals;
• enable circuitry to enable all the charge pump stages in the plurality of charge pump stages in the first mode, and to enable less than all but at least one of the charge pump stages in the plurality of charge pump stages in the second mode
• wherein the enable circuitry includes a plurality of precharge circuits coupled to respective charge pump stages in the plurality of charge pump stages, at least one precharge circuit in the plurality of precharge circuits having a first state allowing a node on the corresponding charge pump stage to fluctuate at a level above the supply potential, and a second state coupling the node to a supply potential without inducing voltage loss of a threshold voltage drop, and thereby decoupling the corresponding stage from preceding stages in the plurality of stages;
• a clock source including a plurality of clock generators, the clock source providing the plurality of clock signals,
• wherein the clock source includes a clock circuit including components tending to cause the frequency of the plurality of clock signals to change according to a second function, where the second function is relatively unresponsive to changes in supply potential;
• and
• circuitry providing control signals to said at least one precharge circuit and to the clock source, so that in the first mode the at least one precharge circuit is in the first state, and in the second mode the at least one precharge circuit is in the second state.

An integrated circuit device, comprising:

• a memory having a first mode for at least one of programming and erasing and a second mode for reading;
• charge pump circuitry coupled to a node in the memory, operable in the first mode and the second mode, the charge pump circuitry including a plurality of charge pump stages, responsive to a plurality of clock signals;
• enable circuitry to enable all the charge pump stages in the plurality of charge pump stages in the first mode, and to enable less than all but at least one of the charge pump stages in the plurality of charge pump stages in the second mode
• wherein the enable circuitry includes a plurality of precharge circuits coupled to respective charge pump stages in the plurality of charge pump stages, at least one precharge circuit in the plurality of precharge circuits having a first state allowing a node on the corresponding charge pump stage to fluctuate at a level above the supply potential, and a second state coupling the node to a supply potential without inducing voltage loss of a threshold voltage drop, and thereby decoupling the corresponding stage from preceding stages in the plurality of stages;
• a clock source including a plurality of clock generators, the clock source providing the plurality of clock signals,
• wherein the clock source includes a clock circuit including components tending to cause the frequency of the plurality of clock signals to change according to a second function, where the second function is relatively unresponsive to changes in supply potential and has a direct relation to changes in temperature;
• and
• circuitry providing control signals to said at least one precharge circuit and to the clock source, so that in the first mode the at least one precharge circuit is in the first state, and in the second mode the at least one precharge circuit is in the second state.

A charge pump apparatus, comprising:

• a plurality of stages including a first stage and a last stage, with one or more intermediate stages arranged in series between the first and last stages;
• each stage in the plurality of stages including a supply node, an output node, and a pass gate, the pass gate having a first state coupling the supply node to the output node, and a second state blocking charge flow from the output node back to the supply node;
• the first stage having its supply node coupled to a supply voltage;
• the intermediate stages having respective supply nodes coupled to the output nodes of the respective preceding stages in the plurality of stages;
• and
• the last stage having its supply node coupled to the output node of its preceding stage in the plurality of stages, and its output node coupled to a load;
• a first plurality of charge boosting circuits coupled to the supply nodes of the intermediate stages and of the last stage;
• a second plurality of charge boosting circuits coupled to the pass gates of the first stage, the intermediate stages, and the last stage;
• a plurality of precharge circuits coupled to the supply nodes of the intermediate stages and the last stages, at least one precharge circuit in the plurality of precharge circuits having a first state allowing the supply node to fluctuate at a level above a supply potential, and a second state coupling the supply node to the supply potential without inducing voltage loss of a threshold voltage drop, and thereby decoupling the corresponding stage from preceding stages in the plurality of stages;
• a clock source including a plurality of clock generators, the clock source providing a plurality of clock signals coupled to the first and second pluralities of charge boosting circuits
• wherein the clock source includes a clock circuit including components tending to cause the frequency of the plurality of clock signals to change according to a first function, where the first function has an inverse relation with change in supply potential and is relatively unresponsive to changes in temperature.

A charge pump apparatus, comprising:

• a plurality of stages including a first stage and a last stage, with one or more intermediate stages arranged in series between the first and last stages;
• each stage in the plurality of stages including a supply node, an output node, and a pass gate, the pass gate having a first state coupling the supply node to the output node, and a second state blocking charge flow from the output node back to the supply node;
• the first stage having its supply node coupled to a supply voltage;
• the intermediate stages having respective supply nodes coupled to the output nodes of the respective preceding stages in the plurality of stages;
• and
• the last stage having its supply node coupled to the output node of its preceding stage in the plurality of stages, and its output node coupled to a load;
• a first plurality of charge boosting circuits coupled to the supply nodes of the intermediate stages and of the last stage;
• a second plurality of charge boosting circuits coupled to the pass gates of the first stage, the intermediate stages, and the last stage;
• a plurality of precharge circuits coupled to the supply nodes of the intermediate stages and the last stage, at least one precharge circuit in the plurality of precharge circuits having a first state allowing the supply node to fluctuate at a level above a supply potential, and a second state coupling the supply node to the supply potential without inducing voltage loss of a threshold voltage drop, and thereby decoupling the corresponding stage from preceding stages in the plurality of stages;
• a clock source providing a plurality of clock signals coupled to the first and second pluralities of charge boosting circuits, and the plurality of clock signals have a frequency which changes according to a first function in a first mode, and have a frequency which changes according to a second function in a second mode, wherein at least one of the first function and the second function is dependent on at least changes in the supply voltage, and at least one of the first function and the second function is dependent on at least changes in temperature;
• and
• circuitry providing control signals to said at least one precharge circuit and to the clock source, so that in the first mode the at least one precharge circuit is in the first state, and in the second mode the at least one precharge circuit is in the second state.

A charge pump apparatus, comprising:

• a multistage charge pump, responsive to a plurality of clock signals, comprising:
• a plurality of stages including a first stage and a last stage, with one or more intermediate stages arranged in series between the first and last stages;
• each stage in the plurality of stages including a supply node, an output node, and a pass gate, the pass gate having a first state coupling the supply node to the output node, and a second state blocking charge flow from the output node back to the supply node;
• the first stage having its supply node coupled to a supply voltage;
• the intermediate stages having respective supply nodes coupled to the output nodes of the respective preceding stages in the plurality of stages;
• and
• the last stage having its supply node coupled to the output node of its preceding stage in the plurality of stages, and its output node coupled to a load;
• a first plurality of charge boosting circuits coupled to the supply nodes of the intermediate stages and of the last stage and to clock signals in the plurality of clock signals;
• and
• a second plurality of charge boosting circuits coupled to the pass gates of the first stage, the intermediate stages, and the last stage and to clock signals in the plurality of clock signals;
• a clock source providing the plurality of clock signals coupled to the multistage charge pump, and the plurality of clock signals have a frequency which changes according to a first function in a first mode, and have a frequency which changes according to a second function in a second mode, wherein the second function is different than the first function, and wherein at least one of the first function and the second function is dependent on at least changes in the supply voltage, and at least one of the first function and the second function is dependent on at least changes in temperature
• wherein the clock source comprises:
• a first clock generator generating a first clock signal of the plurality of clock signals in the first mode;
• and
• a second clock generator generating a second clock signal of the plurality of clock signals in the second mode;
• and
• circuits to enable all the stages in the plurality of stages in the first mode, and to enable less than all the stages in the plurality of stages in the second mode.

An integrated circuit device, comprising:

• a memory having a first mode for at least one of programming and erasing and a second mode for reading;
• charge pump circuitry coupled to a node in the memory, operable in the first mode and the second mode, the charge pump circuitry including a multistage charge pump, responsive to a plurality of clock signals;
• and
• a clock source providing the plurality of clock signals, the plurality of clock signals having a frequency which changes according to a first function in a first mode, and having a frequency which changes according to a second function in a second mode, wherein the second function is different than the first function, and wherein at least one of the first function and the second function is dependent on at least changes in the supply voltage, and at least one of the first function and the second function is dependent on at least changes in temperature,
• wherein the clock source comprises:
• a first clock generator generating a first clock signal of the plurality of clock signals in the first mode;
• and
• a second clock generator generating a second clock signal of the plurality of clock signals in the second mode;
• a plurality of precharge circuits coupled to supply nodes of the intermediate stages and the last stage, at least one precharge circuit in the plurality of precharge circuits having a first state allowing the supply node to fluctuate at a level above the supply potential, and a second state coupling the supply node to a supply potential, and thereby decoupling the corresponding stage from preceding stages in the plurality of stages;
• and
• circuitry providing control signals to said at least one precharge circuit and to the clock source, so that in the first mode the at least one precharge circuit is in the first state, and in the second mode the at least one precharge circuit is in the second state.

A method comprising:

• producing in a first mode of operation, from a first clock generator, a first set of clock signals having a first clock frequency which changes according to a first function;
• producing in a second mode of operation, from a second clock generator, a second set of clock signals having a second clock frequency which changes according to a second function, wherein at least one of the first function and the second function is dependent on at least changes in a power supply voltage, and at least one of the first function and the second function is dependent on at least changes in temperature;
• and
• applying the first set of clock signals to a multistage charge pump having N stages to produce a charge pump output voltage in the first mode of operation and applying the second set of clock signals to a multistage charge pump to produce a charge pump output voltage in the second mode of operation;
• and
• configuring the multistage charge pump so that N stages are enabled in the first mode, and so that less than N stages are enabled in the second mode.