Fabrication of semiconductor structure having N-channel channel-junction field-effect transistor

A method comprising:

• selectively introducing channel-zone-defining n-type semiconductor dopant into a semiconductor body to define an n-type region that includes a surface-adjoining n-type channel zone for a normally off n-channel channel-junction insulated-gate field-effect transistor (“CJIGFET”);
• subsequently providing the semiconductor body with gate dielectric material having parts that respectively substantially constitute (a) a gate dielectric layer for an n-channel surface-channel insulated-gate field-effect transistor (“SCIGFET”) and (b) a gate dielectric layer for the n-channel CJIGFET along its channel zone;
• defining (a) a gate electrode for the n-channel SCIGFET over its gate dielectric layer and (b) a gate electrode for the n-channel CJIGFET over its gate dielectric layer such that each gate dielectric layer extends from the overlying gate electrode to the semiconductor body along largely all lateral area of that gate electrode;
• and
• selectively introducing (a) source/drain-defining n-type semiconductor dopant into p-type material of the semiconductor body to define, for the n-channel SCIGFET, a pair of laterally separated surface-adjoining n-type source/drain zones between which a surface-adjoining p-type channel zone extends along the gate dielectric layer for the n-channel SCIGFET such that its gate dielectric layer overlies its channel zone, partially overlies its source/drain zones, and is separated from its source/drain and channel zones by at least its gate dielectric layer and (b) source/drain-defining n-type semiconductor dopant into the semiconductor body to define, for the n-channel CJIGFET, a pair of laterally separated surface-adjoining n-type source/drain zones between which the n-type channel zone for the n-channel CJIGFET extends such that its gate electrode overlies its channel zone, partially overlies its source/drain zones, and is separated from its source/drain and channel zones by at least its gate dielectric layer and such that the channel zone of the n-channel CJIGFET is more lightly doped than its source/drain zones.