Buffer circuit
AssigneeHewlett-Packard Development Company, L.P.
InventorKing W. Luk
Life of this patent
Estimating the term…
Abstract
Systems, devices, and methods, including logic and/or executable instructions are described in connection with a buffer circuit. One buffer circuit includes a flip-flop based first-in first-out (FIFO) buffer having an input and an output, selection logic coupled in series with the FIFO buffer input, and a random access memory (RAM) FIFO coupled in parallel with the selection logic. The selection logic diverts incoming data to the RAM FIFO after the FIFO buffer is filled to a first capacity level, and reloads the FIFO buffer using data from the RAM FIFO until the RAM FIFO is emptied to a second capacity level. Data is extracted without read data latency from the output of the FIFO buffer as an output of the buffer circuit.
Claims20
A buffer circuit, comprising:
- a flip-flop based first-in first-out (FIFO) buffer having an input and an output;
- selection logic coupled in series with the FIFO buffer input;
- a random access memory (RAM) FIFO coupled in parallel with the selection logic;
- wherein the selection logic is to divert incoming data to the RAM FIFO after the FIFO buffer is filled to a first capacity level such that once the FIFO buffer is filled to the first capacity level the incoming data is no longer sent directly to the FIFO buffer, is to reload the FIFO buffer using data from the RAM FIFO until the RAM FIFO is emptied to a second capacity level, and is to again begin sending the incoming data directly to the FIFO buffer after the FIFO buffer has been emptied to a third capacity level less than the first capacity level and greater than zero;
- wherein the selection logic comprises:
- a multiplexer communicatively connected to an input of the FIFO buffer and to an output of the RAM FIFO;
- a non-multiplexer control to control diversion of the incoming data to the RAM FIFO such that the multiplexer does not control diversion of the incoming data to the RAM FIFO;
- and
- wherein data is extracted without read data latency from the output of the FIFO buffer as an output of the buffer circuit.
A computing system, comprising:
- a processor;
- a memory in communication with the processor;
- and
- a buffering device arranged in a communication path from the memory to the processor, the buffering device having a first-in first-out (FIFO) buffer and a random access memory (RAM) FIFO selectably connected in series with the FIFO buffer;
- wherein the RAM FIFO is selected to be serially connected ahead of the FIFO buffer after the FIFO buffer is filled to a first capacity threshold until the RAM FIFO is emptied to a second capacity threshold such that once the FIFO buffer is filled to the first capacity threshold incoming data is no longer sent directly to the FIFO buffer, and where the FIFO buffer is serially connected ahead of the RAM FIFO after the FIFO buffer has been emptied to a third capacity threshold less than the first capacity threshold and greater than zero, and
- wherein the buffering device comprises:
- a multiplexer communicatively connected to an input of the FIFO buffer and to an output of the RAM FIFO;
- a non-multiplexer control to control diversion of the incoming data to the RAM FIFO such that the multiplexer does not control diversion of the incoming data to the RAM FIFO.
A method of buffering data, the method comprising:
- receiving data to a first-in first-out (FIFO) buffer of a buffer circuit until initially filled to a first capacity threshold such that once the FIFO buffer is filled to the first capacity level the data is not directly received to the FIFO buffer;
- receiving data to a RAM FIFO of the buffer circuit after the FIFO buffer is initially filled to a first capacity threshold until the RAM FIFO is emptied to a second capacity threshold;
- removing data from the RAM FIFO to the FIFO buffer;
- and,
- begin again receiving data to the FIFO buffer after the FIFO buffer has been emptied to a third capacity level less than the first capacity level and greater than zero.
Dependencies are inferred from the claim text.