Power LDMOS transistor

A laterally diffused metal-oxide-semiconductor transistor device comprising:

• a substrate having a first conductivity type;
• a semiconductor layer formed over said substrate and having lower and upper surfaces;
• a source region of the first conductivity type and a lightly-doped drain extension region of the first conductivity type formed in the semiconductor layer proximate the upper surface of said semiconductor layer, said source and lightly-doped drain extension regions being spaced from one another;
• a body region of a second conductivity type formed in said semiconductor layer, said body region forming a channel region between said source and lightly-doped drain extension regions and extending under said source region;
• a conductive gate formed over a gate dielectric layer formed over said channel region;
• a drain contact electrically connecting said lightly-doped drain extension region to said substrate and laterally spaced from said channel region, said drain contact comprising a highly-doped drain contact implant region formed between said substrate and said lightly-doped drain extension region in said semiconductor layer, wherein a upper edge of said highly-doped drain contact implant region is spaced from said upper surface of said semiconductor layer by at least a part of said lightly-doped drain extension region;
• and
• a source contact electrically connecting said source region to said body region.

A laterally diffused metal-oxide-semiconductor transistor device comprising:

• a substrate having a first conductivity type;
• a semiconductor layer formed over said substrate and having lower and upper surfaces;
• a source region of the first conductivity type and a lightly-doped drain extension region of the first conductivity type formed in the semiconductor layer proximate the upper surface of said semiconductor layer, said source and lightly-doped drain extension regions being spaced from one another;
• a body region of a second conductivity type formed in said semiconductor layer, said body region forming a channel region between said source and lightly-doped drain extension regions and extending under said source region;
• a conductive gate formed over a gate dielectric layer formed over said channel region;
• a drain contact electrically connecting said lightly-doped drain extension region to said substrate and laterally spaced from said channel region, said drain contact comprising a highly-doped drain contact implant region formed between said substrate and said lightly-doped drain extension region in said semiconductor layer, at least a portion of said highly-doped drain contact implant region underlying said lightly-doped drain extension region, wherein a upper edge of said highly-doped drain contact implant region is spaced from said upper surface of said semiconductor layer by at least a part of said lightly-doped drain extension region;
• a source contact electrically connecting said source region to said body region;
• an implantation buffer layer in said semiconductor layer formed under said lightly-doped drain extension region and between said body region and said drain contact, said implantation buffer layer comprising dopants of said second conductivity type, wherein said lightly-doped drain extension region and implantation buffer layer are doped with dopant profiles to provide charge balance between said implantation buffer layer and said lightly-doped drain extension region;
• and
• a topside source electrode disposed over said substrate and a bottom side drain electrode disposed under said substrate.