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US 7,587,583 B2Granted
Method and system for processing a “WIDE” opcode when it is not used as a prefix for an immediately following opcode
AssigneeTexas Instruments Incorporated
InventorGerard Chauvel
Life of this patent
Estimating the term…
Abstract
Methods and systems are provided for the selective use of a Java WIDE opcode as a prefix as defined in the instruction set of the Java virtual machine or performing a task assigned to the Java WIDE opcode. A Java WIDE opcode is fetched, a determination is made as to whether the Java WIDE opcode is to be used as a prefix, and when the Java WIDE opcode is not to be used as a prefix, a task assigned to the Java WIDE opcode is performed.
Claims9
A method of operating a system including a stack machine and a processor that uses a stream of bytecodes for operation, the method comprising:
- A. fetching a WIDE opcode from the stream of bytecodes;
- B. determining whether the WIDE opcode is to be used as a prefix for an opcode that immediately follows the WIDE opcode in the stream of bytecodes;
- and
- C. when the WIDE opcode is not to be used as a prefix, performing a task assigned to the WIDE opcode, the performing a task including:
- i. using the WIDE opcode as an index into a vector table to locate an entry corresponding to the WIDE opcode;
- ii. when a bit in the entry is asserted, initiating direct execution of the WIDE opcode;
- and
- iii. when the bit in the entry is not asserted, triggering a micro-sequence referenced in the entry.
5 more elements
A processor comprising:
- A. fetch logic configured to retrieve a WIDE opcode from a stream of bytecodes stored in a memory;
- B. decode logic coupled to the fetch logic, wherein the decode logic is configured to:
- i. determine, when the WIDE opcode is retrieved, whether the WIDE opcode is to be used as a prefix for an opcode that immediately follows the WIDE opcode in the stream of bytecodes;
- and
- ii. when the WIDE opcode is not to be used as a prefix, cause performance of a task assigned to the WIDE opcode;
- and
- C. a vector table accessible by the decode logic, the vector table including an entry corresponding to the WIDE opcode, the decode logic configured to cause performance of a task assigned to the WIDE opcode by:
- i. using the WIDE opcode as an index into the vector table to locate the entry,
- ii. initiating direct execution of the WIDE opcode when a bit in the entry is asserted, and
- iii. triggering a micro-sequence referenced in the entry when the bit in the entry is not asserted.
7 more elements
A system comprising:
- A. a first processor;
- B. a memory coupled to the first processor, the memory configured to store a stream of bytecodes;
- C. a second processor coupled to the first processor and the memory, the second processor including:
- i. fetch logic configured to retrieve a WIDE opcode from the stream of bytecodes stored in the memory;
- ii. decode logic coupled to the fetch logic, wherein the decode logic is configured to:
- a. determine, when the WIDE opcode is retrieved, whether the WIDE opcode is to be used as a prefix for an opcode that immediately follows the WIDE opcode in the stream of bytecodes;
- and
- b. when the WIDE opcode is not to be used as a prefix, cause performance of a task assigned to the WIDE opcode;
- iii. a vector table coupled to and accessible by the decode logic, the vector table including an entry corresponding to the WIDE opcode;
- and
- iv. wherein the decode logic is further configured to cause performance of a task assigned to the WIDE opcode by:
- a. using the WIDE opcode as an index into the vector table to locate the entry,
- b. initiating direct execution of the WIDE opcode when a bit in the entry is asserted, and
- c. triggering a micro-sequence referenced in the entry when the bit in the entry is not asserted.
11 more elements
Dependencies are inferred from the claim text.