Memory mapping for single and multi-processing implementations of code generated from a block diagram model
AssigneeThe MathWorks, Inc.
InventorsDavid Koh, Zijad Galijasevic
Life of this patent
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Abstract
Methods and systems are provided for automatically generating code from a graphical model representing a design to be implemented on components of a target computational hardware device. During the automatic code generating process, a memory mapping is automatically determined and generated to provide an optimization of execution of the program on the target device. The optimized memory mapping is incorporated into building the program executable from the automatically generated code of the graphical model.
Claims57
In an electronic device, a method for determining a memory mapping for executable instructions generated from a graphical model to execute on a computational hardware device having one or more processors, the method comprising:
- receiving program information comprising a description of one or more program segments, each program segment comprising one of a code segment and a data segment of executable instructions generated from a graphical model;
- receiving memory information comprising a description of one or more memory elements of the computational hardware device;
- and
- using the program information and the memory information to determine a memory mapping that provides for executing the executable instructions in a desired manner on the computational hardware device, the memory mapping identifying placement of the one or more program segments to portions of the one or more memory elements.
In an electronic device, a method for generating code from a graphical model to incorporate a memory mapping for executable instructions to run on a computational hardware device, the method comprising:
- initiating an automatic generation of code from a graphical model to provide executable instructions to run on a computational hardware device having one or more processors;
- assigning one of a code segment and a data segment of the generated code to a named memory section to be associated with a memory element of the computational hardware device, the code and data segment representing at least a portion of functionality of the graphical model;
- obtaining a memory mapping providing an optimization of execution of the executable instructions on the computational hardware device, the memory mapping describing a placement of one of the code segment and the data segment to a portion of a memory element of the computational hardware device;
- and
- providing a linker file to associate, in building an executable from the executable instructions, the named memory section with the portion of the memory element as determined by the memory mapping.
In an electronic device, a method for automatically generating code for a graphical model and determining a memory mapping for the execution of instructions on a computational hardware device having one or more processors, the method comprising:
- initiating an automatic generation of code from a graphical model to provide executable instructions to execute on the computational hardware device, the automatic generation of code providing one or more compiler directives to place one of a code segment and a data segment of the executable instructions into a named memory section, the code segment and the data segment representing at least a portion of functionality of the graphical model;
- obtaining program information comprising a description of one or more code and data segments of the executable instructions;
- obtaining memory information comprising a description of one or more memory elements of the computational hardware device;
- determining a memory mapping providing for executing the executable instructions in a desired manner on the computational hardware device, the memory mapping automatically generated from a comparison between the program information and the memory information to determine a placement of one or more code and data segments of the executable instructions to portions of the one or more memory elements of the computational hardware device;
- and
- providing a linker file to associate the named memory section with the portion of the memory element as determined by the memory mapping.
A system to generate executable instructions for a graphical model and to determine a memory mapping for the execution of the executable instructions on a computational hardware device, the system comprising:
- an automatic code generator generating code from a graphical model to provide executable instructions to execute on a computational hardware device having one or more processors, the automatic code generator providing a compiler directive to associate one of a code segment and a data segment of the executable instructions with a named memory section to be associated with a memory element of the computational hardware device, the code segment and the data segment representing at least a portion of functionality of the graphical model;
- and
- a memory mapping generator obtaining program information descriptive of one of the code and data segment, and memory information descriptive of the one or more memory elements of the computational hardware device to automatically generate a memory mapping that provides for executing the executable instructions in a desired manner on the computational hardware device,
- wherein the memory mapping generator automatically generates the memory mapping from a comparison between the program information and the memory information to determine a placement of one or more code and data segments of the executable instructions to portions of the one or more memory elements of the computational hardware device.
A computer-readable medium storing computer-executable instructions, the instructions when executed in a processor of a computer causing the computer to perform a method of determining a memory mapping for executable instructions generated from a graphical model to execute on a computational hardware device having one or more processors, the method comprising:
- receiving program information comprising a description of one or more program segments, each program segment comprising one of a code segment and a data segment of executable instructions generated from a graphical model;
- receiving memory information comprising a description of one or more memory elements of the computational hardware device;
- and
- using the program information to the memory information to determine a memory mapping that provides for executing the executable instructions in a desired manner on the computational hardware device, the memory mapping identifying placement of the one or more program segments to portions of the one or more memory elements.
A computer-readable medium storing computer-executable instructions, the instructions when executed in a processor of a computer causing the computer to perform a method of generating code from a graphical model to incorporate a memory mapping for executable instructions to run on a computational hardware device, the method comprising:
- initiating an automatic generation of code for a graphical model to provide executable instructions to run on a computational hardware device having one or more processors;
- assigning one of a code segment and a data segment of the generated code to a named memory section to be associated with a memory element of the computational hardware device, the code and data segment representing at least a portion of functionality of the graphical model;
- obtaining a memory mapping providing an optimization of execution of the executable instructions on the computational hardware device, the memory mapping describing a placement of one of the code segment and the data segment to a portion of a memory element of the computational hardware device;
- and
- providing a linker file to associate, in building an executable from the executable instructions, the named memory section with the portion of the memory element as determined by the memory mapping.
A computer-readable medium storing computer-executable instructions, the instructions when executed in a processor of a computer causing the computer to perform a method of automatically generating code and determining a memory mapping for executing instructions on a computational hardware device having one or more processors, the method comprising:
- initiating an automatic generation of code from a graphical model to provide executable instructions to execute on the computational hardware device, the automatic generation of code providing one or more compiler directives to place one of a code segment and a data segment of the executable instructions into a named memory section, the code segment and the data segment representing at least a portion of functionality of the graphical model;
- obtaining program information comprising a description of one or more code and data segments of the executable instructions;
- obtaining memory information comprising a description of one or more memory elements of the computational hardware device;
- determining a memory mapping providing for executing the executable instructions in a desired manner on the computational hardware device, the memory mapping automatically generated from a comparison between the program information and the memory information to determine a placement of one or more code and data segments of the executable instructions to portions of the one or more memory elements of the computational hardware device;
- and
- providing a linker file to associate the named memory section with the portion of the memory element as determined by the memory mapping.
In an electronic device, a method for determining a memory mapping for executable instructions to execute on a computational hardware device, the method comprising:
- receiving program information comprising a description of one or more program segments, each program segment comprising one of a code segment and a data segment of executable instructions;
- receiving memory information comprising a description of one or more memory elements of a computational hardware device having one or more processors;
- and
- comparing, by a memory mapping generator, the program information to the memory information to automatically determine a memory mapping that provides for executing the executable instructions in a desired manner on the computational hardware device, the memory mapping identifying placement of the one or more program segments to portions of the one or more memory elements.
In an electronic device, a method for providing a memory mapping for executable instructions to execute on a computational hardware device having one or more processors, the method comprising:
- receiving program information identifying one or more program segments, each program segment comprising one of a code segment and a data segment of executable instructions;
- receiving memory information identifying one or more memory elements of a computational hardware device, at least a portion of one of the memory elements is identified by a user;
- and
- generating a memory mapping identifying placement of the one or more program segments to portions of the one or more memory elements, the memory mapping providing for executing the executable instructions in a user desired manner on the computational hardware device.
Dependencies are inferred from the claim text.