Method and apparatus for debugging embedded systems having read only memory
AssigneeAltera Corporation
InventorsKerry Veenstra, Tim Allen
Life of this patent
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AssigneeAltera Corporation
InventorsKerry Veenstra, Tim Allen
Estimating the term…
A programmable logic device (PLD) is provided. The PLD includes a microprocessing unit (MPU) and a memory region functioning in a read only state. A Joint Test Action Group (JTAG) debug module in communication with the memory region is included in the PLD. The JTAG debug module is able to detect a breakpoint causing an interruption of a processing sequence executed by the MPU. Write control circuitry capable of issuing a signal enabling the memory region to transition from the read only state disallowing writes to a second state accepting write data from the MPU is included in the JTAG debug circuitry. In one embodiment, the write control circuitry issues the signal in response to a breakpoint induced either through hardware or software. A method of debugging a PLD is also provided.
A method for debugging an integrated circuit (IC), comprising method operations of:
A tangible computer readable medium having program instructions for debugging an IC, comprising:
An integrated circuit (IC), comprising:
Dependencies are inferred from the claim text.