Logic synthesis of multi-level domino asynchronous pipelines

A computer-implemented method for optimizing a circuit design, comprising:

• generating a gate level circuit description corresponding to the circuit design, the gate level circuit description comprising a plurality of pipelines across a plurality of levels, the plurality of pipelines including a first pipeline comprising two paths which diverge at a fork stage and converge at a join stage;
• and
• using a linear programming technique, adding a first number of buffers to selected stages of the pipelines such that the pipelines are balanced, at least one performance constraint is satisfied, an objective function characterizing the circuit design is minimized, and each pipeline has at least one gate in each pipeline stage through which it passes, wherein the two paths of the first pipeline include different numbers of cells.