US 7,584,448 B1Granted

Constructing a model of a programmable logic device

AssigneeXilinx, Inc.

InventorsBart Reynolds, Keith R. Bean, Daniel P. Kirkwood, James F. Barei, Benjamin D. Ralston

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Abstract

A processor-implemented method is provided for constructing a model of a programmable logic device (PLD) design. A netlist is input that describes the PLD design. An identification is input of programmable tile modules that include a programmable resource, which is either programmable interconnect or programmable logic. A first characterization data is input for sub-modules of the programmable tile modules for the programmable resource. For each programmable tile module, the routing arcs of each programmable interconnect are generated. A second characterization data is input for a configuration memory cell module of the PLD design. A third characterization data is input for a configuration control module of the PLD design. A first map is generated that links each routing arc to a bit of configuration data for programming the programmable interconnect. A second map is generated that links each logic function to a bit of configuration data for programming the programmable logic.

Claims20

Dependent claims

A processor-implemented method for constructing a model of a programmable logic device (PLD) design, comprising:

inputting a netlist that describes the PLD design, the netlist including a plurality of instances of a plurality of modules, and the modules including a plurality of programmable tile modules and the instances including a plurality of tile instances of the programmable tile modules;
inputting an identification of each of the programmable tile modules, each programmable tile module including at least one programmable resource, each programmable resource being one of a programmable interconnect resource configurable to implement a plurality of routing arcs and a programmable logic resource configurable to implement a plurality of logic functions;
generating a first map from the netlist, the first map linking each of the routing arcs to at least one bit of configuration data for programming the programmable interconnect resources of the programmable tile modules;
and
generating a second map from the netlist, the second map linking each of the logic functions to at least one bit of configuration data for programming the programmable logic resources of the programmable tile modules
wherein the inputting a netlist, the inputting an identification, the generating a first map, and the generating a second map are implemented on the processor.

3 more elements

A program storage medium, comprising:

a processor-readable device configured with instructions for constructing a model of a programmable logic device (PLD) design, wherein execution of the instructions by one or more processors causes the one or more processors to perform operations including,
inputting a netlist that describes the PLD design, the netlist including a plurality of instances of a plurality of modules, and the modules including a plurality of programmable tile modules and the instances including a plurality of tile instances of the programmable tile modules;
inputting an identification of each of the programmable tile modules, each programmable tile module including at least one programmable resource, each programmable resource being one of a programmable interconnect resource configurable to implement a plurality of routing arcs and a programmable logic resource configurable to implement a plurality of logic functions;
inputting first characterization data for a plurality of sub-modules of the programmable tile modules for the programmable resources;
for each programmable tile module identified by the identification, generating from the netlist and the first characterization data the routing arcs of each programmable interconnect resource of the programmable tile module;
inputting second characterization data for at least one configuration-memory-cell module of the PLD design;
inputting third characterization data for at least one configuration control module of the PLD design;
and
generating a first map from the netlist and the second and third characterization data, the first map linking each routing arc to at least one bit of configuration data for programming the programmable interconnect resources of the programmable tile modules;
and
generating a second map from the netlist and the second and third characterization data, the second map linking each logic function to at least one bit of configuration data for programming the programmable logic resources of the programmable tile modules.

8 more elements

Dependencies are inferred from the claim text.