PLD architecture for flexible placement of IP function blocks

A programmable logic device, comprising:

• a plurality of logic elements arranged in an array of rows and columns;
• at least one IP function block that is incorporated into a location in the array of logic elements spanning a plurality of adjacent and intersecting rows and columns, wherein the incorporation of the IP function block displaces logic elements from that location;
• and
• interface circuitry operable to interconnect the IP function block to the logic elements, wherein the interface circuitry is located adjacent to at least a portion of the IP function block between the IP function blocks and the logic elements.