Method for generating optimized constraint systems for retimable digital designs

A method for generating timing constraints, comprising the steps of:

• describing a digital circuit using a hardware description language (HDL);
• preparing a digital circuit representation from said HDL description;
• removing flip-flops from said digital circuit representation using a computer;
• replacing said removed flip-flops with negative delay elements;
• and
• where some of the negative delay elements comprise buffers, said buffers having a load capacitance representing an average or weighted-average load capacitance taken over inputs of all gates and flip-flop D pins in a target technology library.

A method for generating timing constraints, comprising operations of:

• describing a digital circuit using a hardware description language (HDL);
• preparing a digital circuit representation from said HDL description;
• replacing flip-flops in said digital circuit representation with negative delay elements using a computer;
• wherein said negative-time elements are implemented by buffers having a delay −T, where T is a delay equal to a flip-flop's clock period less a predetermined flip-flop delay;
• describing a value of T using a capacitance/delay curve representing a composite of gates in a target technology library, Q pins of flip-flops in said target technology library, and a series of increasingly powerful buffer trees;
• wherein said curve is first computed, then it is offset by setting a delay corresponding to a predetermined load capacitance to −T;
• whereby a larger capacitive load results in a longer delay;
• and
• whereby if a near-zero load is imposed a delay is −(T+t), where t is a (positive) difference in delay between a predetermined load and a lesser load.

A method for generating timing constraints, comprising the steps of:

• a step for describing a digital circuit using a hardware description language (HDL);
• a step for preparing a digital circuit representation from said HDL description;
• a step for removing flip-flops from said digital circuit representation and replacing said removed flip-flops with negative delay elements;
• and
• a step for breaking any feedback paths in the digital circuit representation by inserting dummy flip-flops clocked by clocks all having a prescribed period using a computer.

A computer readable storage device containing one or more programs executable by a computer to perform operations comprising:

• receiving a description of a digital circuit using a hardware description language (HDL) and preparing a digital circuit representation from said HDL description;
• removing flip-flops from said digital circuit representation and replacing said removed flip-flops with negative delay elements;
• and
• breaking any feedback paths in the digital circuit representation by inserting dummy flip-flops clocked by clocks all having a prescribed period.

A computer readable storage device containing one or more programs executable by a computer to perform operations comprising:

• receiving a description of a digital circuit using a hardware description language (HDL) and preparing a digital circuit representation from said HDL description;
• replacing flip-flops in said digital circuit representation with negative delay elements;
• wherein said negative-time elements are implemented by buffers having a delay −T, where T is a delay equal to a flip-flop's clock period less a predetermined flip-flop delay;
• describing a value of T using a capacitance/delay curve representing a composite of gates in a target technology library, Q pins of flip-flops in said target technology library, and a series of increasingly powerful buffer trees;
• wherein said curve is first computed, then it is offset by setting a delay corresponding to a predetermined load capacitance to −T;
• whereby a larger capacitive load results in a longer delay;
• and
• whereby if a near-zero load is imposed a delay is −(T+t), where t is a (positive) difference in delay between a predetermined load and a lesser load.

A computer driven system for generating timing constraints, comprising:

• digital data storage;
• coupled to the digital data storage, a digital data processor programmed to perform operations comprising:
• receiving a description of a digital circuit using a hardware description language (HDL) and preparing a digital circuit representation from said HDL description;
• removing flip-flops from said digital circuit representation and replacing said removed flip-flops with negative delay elements;
• and
• breaking any feedback paths in the digital circuit representation by inserting dummy flip-flops clocked by clocks all having a prescribed period.

A computer readable storage device containing one or more programs executable by a computer to perform operations comprising:

• receiving a description of a digital circuit using a hardware description language (HDL) and preparing a digital circuit representation from said HDL description;
• removing flip-flops from said digital circuit representation and replacing said removed flip-flops with negative delay elements;
• and
• where some of the negative delay elements comprise buffers, said buffers having a load capacitance representing an average or weighted-average load capacitance taken over inputs of all gates and flip-flop D pins in a target technology library.

A computer driven system for generating timing constraints, comprising:

• digital data storage;
• coupled to the digital data storage, a digital data processor programmed to perform operations comprising:
• receiving a description of a digital circuit using a hardware description language (HDL) and preparing a digital circuit representation from said HDL description;
• removing flip-flops from said digital circuit representation and replacing said removed flip-flops with negative delay elements;
• and
• where some of the negative delay elements comprise buffers, said buffers having a load capacitance representing an average or weighted-average load capacitance taken over inputs of all gates and flip-flop D pins in a target technology library.