Method for rapid estimation of layout-dependent threshold voltage variation in a MOSFET array

An automated method for estimating layout-induced variations in threshold voltage in an integrated circuit layout, comprising the steps of:

• selecting a diffusion area within the layout for analysis;
• identifying Si/STI edges on the selected area;
• identifying channel areas and their associated gate/Si edges;
• determining threshold voltage variations in each identified channel area, including the steps of
• calculating, by a computer, threshold voltage variations due to effects in a longitudinal direction;
• calculating, by the computer, threshold voltage variations due to effects in a transverse direction;
• and
• combining, by the computer, the longitudinal and transverse variations to provide an overall variation,
• wherein calculating threshold voltage variations includes multiplying the maximum threshold voltage variation by a decay function,
• wherein threshold voltage variations due to effects in a longitudinal direction are calculated according to a decay function,
• λi(x)=1/((xi/α)βi+εi),
• where αi, βi and εi, are process and material-related factors;
• and
• threshold voltage variations due to effects in a transverse direction are calculated according to the complementary error function, erfc.

A system for automated estimation of layout-induced variations in threshold voltage in an integrated circuit layout, comprising:

• a digital computer, including a processor, display means and data storage means storing a computer program configured to perform the steps of
• selecting a diffusion area within the layout for analysis;
• identifying Si/STI edges on the selected area;
• identifying channel areas and their associated gate/Si edges;
• determining threshold voltage variations in each identified channel area, including the steps of
• calculating threshold voltage variations due to effects in a longitudinal direction;
• calculating threshold voltage variations due to effects in a transverse direction;
• and
• combining the longitudinal and transverse variations to provide an overall variation,
• wherein calculating threshold voltage variations includes multiplying the maximum threshold voltage variation by a decay function of the form
• λi(r)=1/((xi/α)βi+εi),
• where αi, βi and εi, are process and material-related factors.

A system for automated estimation of layout-induced variations in threshold voltage in an integrated circuit layout, comprising:

• a digital computer, including a processor, display means and data storage means storing a computer program configured to perform the steps of
• selecting a diffusion area within the layout for analysis;
• identifying Si/STI edges on the selected area;
• identifying channel areas and their associated gate/Si edges;
• determining threshold voltage variations in each identified channel area, including the steps of
• calculating threshold voltage variations due to effects in a longitudinal direction;
• calculating threshold voltage variations due to effects in a transverse direction;
• and
• combining the longitudinal and transverse variations to provide an overall variation,
• wherein calculating threshold voltage variations includes multiplying the maximum threshold voltage variation by a decay function,
• wherein threshold voltage variations due to effects in a longitudinal direction are calculated according to a decay function,
• λi(r)=1/((xi/α)βi+εi),
• where αi, βi and εi, are process and material-related factors;
• and
• threshold voltage variations due to effects in a transverse direction are calculated according to the complementary error function, erfc.

Data storage means for use with a digital computer having a processor, the data storage means having stored thereon a computer program configured to perform the steps of

• selecting a diffusion area within the layout for analysis;
• identifying Si/STI edges on the selected area;
• identifying channel areas and their associated gate/Si edges;
• determining threshold voltage variations in each identified channel area, including the steps of
• calculating threshold voltage variations due to effects in a longitudinal direction;
• calculating threshold voltage variations due to effects in a transverse direction;
• and
• combining the longitudinal and transverse variations to provide an overall variation,
• wherein calculating threshold voltage variations includes multiplying the maximum threshold voltage variation by a decay function of the form
• λi(r)=1/((xi/α)βi+εi),
• where αi, βi and εi, are process and material-related factors, and r is a distance in either the X or Y direction.

Data storage means for use with a digital computer having a processor, the data storage means having stored thereon a computer program configured to perform the steps of

• selecting a diffusion area within the layout for analysis;
• identifying Si/STI edges on the selected area;
• identifying channel areas and their associated gate/Si edges;
• determining threshold voltage variations in each identified channel area, including the steps of
• calculating threshold voltage variations due to effects in a longitudinal direction;
• calculating threshold voltage variations due to effects in a transverse direction;
• and
• combining the longitudinal and transverse variations to provide an overall variation,
• wherein calculating threshold voltage variations includes multiplying the maximum threshold voltage variation by a decay function,
• wherein threshold voltage variations due to effects in a longitudinal direction are calculated according to a decay function,
• λi(x)=1/((xi/α)βi+εi),
• where αi, βi and εi, are process and material-related factors;
• and
• threshold voltage variations due to effects in a transverse direction are calculated according to the complementary error function, erfc.