Clash-free irregular-repeat-accumulate code

A computer-implemented method for performing data decoding comprising:

• receiving a sequence of encoded bits;
• decoding the sequence of encoded bits in accordance with a parity check matrix (H-matrix) to generate a sequence of decoded bits;
• wherein the H-matrix is capable of being partitioned into a first matrix and a second, matrix, the first matrix being a dual-diagonal matrix, the second matrix comprising one or more vertically stacked sub-matrices, each sub-matrix consisting of a plurality of columns, each column having a column weight of no more than 1;
• wherein the second matrix is capable of being expressed as a product of a parity check matrix, an interleaver permutation matrix, and a repeat block matrix, and the interleaver permutation matrix satisfies a clash-free interleaver constraint;
• and
• outputting the sequence of decoded bits.

An apparatus for performing data encoding comprising:

• an input interface for receiving a sequence of data bits;
• an encoder coupled to the input interface capable of encoding the sequence of data bits in accordance with a parity check matrix (H-matrix) to generate a sequence of encoded bits;
• wherein the H-matrix is capable of being partitioned into a first matrix and a second matrix, the first matrix being a dual-diagonal matrix, the second matrix comprising one or more vertically stacked sub-matrices, each sub-matrix consisting of a plurality of columns, each column having a column weight of no more than 1;
• wherein the second matrix is capable of being expressed as a product of a parity check matrix, an interleaver permutation matrix, and a repeat block matrix, and the interleaver permutation matrix satisfies a clash-free interleaver constraint;
• and
• an output interface couple to the encoder for outputting the sequence of encoded bits.

A apparatus for performing data decoding comprising:

• an input interface for receiving a sequence of encoded bits;
• a decoder coupled to the input interface capable of decoding the sequence of encoded bits in accordance with a parity check matrix (H-matrix) to generate a sequence of decoded bits;
• wherein the H-matrix is capable of being partitioned into a first matrix and a second matrix, the first matrix being a dual-diagonal matrix, the second matrix comprising one or more vertically stacked sub-matrices, each sub-matrix consisting of a plurality of columns, each column having a column weight of no more than 1;
• wherein the second matrix is capable of being expressed as a product of a parity check matrix, an interleaver permutation matrix, and a repeat block matrix, and the interleaver permutation matrix satisfies a clash-free interleaver constraint;
• and
• an output interface coupled to the decoder for outputting the sequence of decoded bits.

A system for performing data encoding comprising:

• means for receiving a sequence of data bits;
• means for encoding the sequence of data bits in accordance with a parity check matrix (H-matrix) to generate a sequence of encoded bits;
• wherein the H-matrix is capable of being partitioned into a first matrix and a second matrix, the first matrix being a dual-diagonal matrix, the second matrix comprising one or more vertically stacked sub-matrices, each sub-matrix consisting of a plurality of columns, each column having a column weight of no more than 1;
• wherein the second matrix is capable of being expressed as a product of a parity check matrix, an interleaver permutation matrix, and a repeat block matrix, and the interleaver permutation matrix satisfies a clash-free interleaver constraint;
• and
• means for outputting the sequence of encoded bits.