System and method for pseudo-random test pattern memory allocation for processor design verification and validation

An information handling system comprising:

• one or more processors;
• a memory accessible by the processors;
• one or more nonvolatile storage devices accessible by the processors;
• and
• a set of instructions stored in the memory, wherein one or more of the processors executes the set of instructions in order to perform actions of:
• selecting a first instruction;
• pseudo-randomly identifying a first page table memory address from a page table memory area to associate with the first instruction;
• building a first test pattern using the first instruction and the first page table memory address;
• selecting a second instruction;
• pseudo-randomly identifying a second page table memory address from the page table memory area to associate with the second instruction;
• building a second test pattern using the second instruction and the second page table memory address;
• dispatching the first test pattern to a first thread and dispatching the second test pattern to a second thread;
• and
• executing the first and the second test patterns in the first thread and the second thread.

A computer program product stored on a computer operable media, the computer operable media containing instructions for execution by a computer, which, when executed by the computer, cause the computer to implement a method of processing test patterns, the method comprising:

• selecting a first instruction;
• pseudo-randomly identifying a first page table memory address from a page table memory area to associate with the first instruction;
• building a first test pattern using the first instruction and the first page table memory address;
• selecting a second instruction;
• pseudo-randomly identifying a second page table memory address from the page table memory area to associate with the second instruction;
• building a second test pattern using the second instruction and the second page table memory address;
• dispatching the first test pattern to a first thread and dispatching the second test pattern to a second thread;
• and
• executing the first and the second test patterns in the first thread and the second thread.