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US 7,584,392 B2Granted
Test compaction using linear-matrix driven scan chains
AssigneeCadence Design Systems, Inc.
InventorSandeep Bhatia
Life of this patent
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Abstract
A scan technique using linear matrix to drive scan chains is used, along with an ATPG, to constraint scan test vectors to be generated through the linear matrix. The linear matrix scan technique reduces the test application time and the amount of test vector data by several orders of magnitude over conventional techniques, without reducing fault coverage.
Claims12
An apparatus comprising:
- means for dividing p pins of an integrated circuit into n groups;
- means for logically associating the pins of each group through an ExOR matrix;
- and
- means for driving a plurality of scan chains in the integrated circuit with the logically associated pins, wherein the plurality of scan chains are driven by ExORing the pins from the n groups, and the ExOR matrix is configured such that the number of pins logically associated through the ExOR matrix is less than the number of scan chains coupled to the ExOR matrix.
1 more element
A computer readable memory having stored thereon a computer program which, when executed by a processor, causes the execution of a process, the memory comprising:
- code for dividing p pins of an integrated circuit into n groups;
- code for logically associating the pins of each group through an ExOR matrix;
- code for driving a plurality of scan chains in the integrated circuit with the logically associated pins, wherein the plurality of scan chains are driven by ExORing the pins from the n groups, and the ExOr matrix is configured such that the number of pins logically associated through the ExOR matrix is less than the number of scan chains coupled to the ExOR matrix;
- and
- code for storing a result of a logical operation performed by the ExOR matrix.
2 more elements
A method comprising:
- dividing p pins of an integrated circuit into n groups;
- logically associating the pins of each group through an ExOR matrix;
- and
- driving a plurality of scan chains in the integrated circuit with the logically associated pins, wherein the plurality of scan chains are driven by ExORing the pins from the n groups, and the ExOR matrix is configured such that the number of pins logically associated through the ExOR matrix is less than the number of scan chains coupled to the ExOR matrix.
1 more element
Dependencies are inferred from the claim text.