Turbo decoding apparatus and method

A turbo decoding apparatus in a communication system, comprising:

• a unidirectional shift register having an input terminal for data input and an output terminal for data output, the unidirectional shift register forming bit streams of a first length by sequentially receiving and shifting input data bits via the input terminal and then sequentially outputting the formed bit streams of the first length via the output terminal;
• a memory buffer including one or more bidirectional shift registers having a first terminal and a second terminal for data input/output, the input data bits being divided into groups each comprised of bits of a second length which is ½ of the first length, the bidirectional shift register forming bit streams of the second length by sequentially receiving and shifting bits of odd-numbered groups among the divided groups via the first terminal and then sequentially outputting the formed bit streams via the first terminal;
• and forming bit streams of the second length by sequentially receiving and shifting bits of even-numbered groups among the divided groups via the second terminal and then sequentially outputting the formed bit streams via the second terminal;
• a first metric calculation section for receiving output bits of the respective shift registers, and calculating corresponding delta metrics;
• a second metric calculation section for receiving a delta metric from the first metric calculation section corresponding to the unidirectional shift register, and calculating an alpha metric;
• a third metric calculation section for receiving delta metrics from the first metric calculation section corresponding to the bidirectional shift registers, and calculating beta metrics;
• a fourth metric calculation section for receiving the alpha metric, also receiving a multiplexing result of the beta metrics, and calculating Log Likelihood Ratio (LLR) values corresponding to the respective shift registers;
• and
• a Soft-In Soft-Out (SISO) decoder including a subtraction section for subtracting an output of the unidirectional shift register from the respective LLR values, and outputting the subtraction result for interleaving/deinterleaving.

A turbo decoding apparatus in a communication system, comprising:

• one or more first stage's bidirectional shift registers having a first terminal and a second terminal for data input/output, input data bits being divided into groups each comprised of bits of a predetermined length, the first stage's bidirectional shift registers forming bit streams of the length by sequentially receiving and shifting bits of odd-numbered groups among the divided groups via the first terminal and then sequentially outputting the formed bit streams via the first terminal;
• and forming bit streams of the length by sequentially receiving and shifting bits of even-numbered groups among the divided groups via the second terminal and then sequentially outputting the formed bit streams via the second terminal;
• a memory buffer including a second stage's bidirectional shift register having a third terminal and a fourth terminal for data input/output, the second stage's bidirectional shift register forming bit streams of the length by sequentially receiving and shifting bits sequentially output via the first terminal, via the third terminal, and then sequentially outputting the formed bit streams via the third terminal;
• and forming bit streams of the length by sequentially receiving and shifting bits sequentially output via the second terminal, via the fourth terminal, and then sequentially outputting the formed bit streams via the fourth terminal;
• a first metric calculation section for receiving output bits of the respective shift registers, and calculating corresponding delta metrics;
• a second metric calculation section for receiving a delta metric from the first metric calculation section corresponding to the unidirectional shift register, and calculating an alpha metric;
• a third metric calculation section for receiving delta metrics from the first metric calculation section corresponding to the bidirectional shift registers, and calculating beta metrics;
• a fourth metric calculation section for receiving the alpha metric, also receiving a multiplexing result of the beta metrics, and calculating Log Likelihood Ratio (LLR) values corresponding to the respective shift registers;
• and
• a Soft-In Soft-Out (SISO) decoder including a subtraction section for subtracting an output of a unidirectional shift register from the respective LLR values, and outputting the subtraction result for interleaving/deinterleaving.

A method of providing a memory buffer for receiving a frame comprised of sequential input symbols and providing the input symbols to an N-window mode Soft-In Soft-Out (SISO) decoder having a window size of W symbols, the method comprising the steps of:

• sequentially shifting and storing 2NW serial symbols from an input terminal of a first shift register in a predetermined direction;
• sequentially outputting the shifted symbols via a output terminal of the first shift register;
• sequentially activating or initializing N second shift registers at intervals of W symbols from serial symbols received at the input terminal of the first shift register, wherein each of the second shift registers includes a clock input terminal, first and second input terminals, first and second output terminals, and select terminals;
• receiving at each of the second shift registers first NW symbols among the serial symbols after its activation;
• shifting and storing the received symbols in the predetermined direction, thereafter, each of the second shift registers receiving second NW symbols via its second input terminal;
• and
• shifting and storing the received symbols in the opposite direction of the predetermined direction, and simultaneously, serially outputting the stored first NW symbols via its first output terminal, thereafter, each of the second shift registers receiving third NW symbols via the first input terminal, shifting and storing the received symbols in the predetermined direction, and simultaneously, serially outputting the stored second NW symbols via its second output terminal,
• wherein N refers to an integer and a number of windows, W refers to an integer and a size of windows, NW refers to N times W and a length of data bit streams, and 2NW refers to two (2) times NW.

A method of providing a turbo decoding in a communication system, the method comprising:

• forming at a unidirectional shift register having an input terminal for data input and an output terminal for data output, bit streams of a first length by sequentially receiving and shifting input data bits via the input terminal and then sequentially outputting the formed bit streams of the first length via the output terminal;
• dividing input data into groups the input data each comprised of bits of a second length which is ½ of the first length, at a memory buffer including one or more bidirectional shift registers having a first terminal and a second terminal for data input/output, the bidirectional shift register forming bit streams of the second length by sequentially receiving and shifting bits of odd-numbered groups among the divided groups via the first terminal and then sequentially outputting the formed bit streams via the first terminal;
• and forming bit streams of the second length by sequentially receiving and shifting bits of even-numbered groups among the divided groups via the second terminal and then sequentially outputting the formed bit streams via the second terminal;
• receiving output bits of the respective shift registers, and calculating corresponding delta metrics at a first metric calculation section;
• receiving a delta metric from the first metric calculation section corresponding to the unidirectional shift register, and calculating an alpha metric at a second metric calculation section;
• receiving delta metrics from the first metric calculation section corresponding to the bidirectional shift registers, and calculating beta metrics at a third metric calculation section;
• receiving the alpha metric, also receiving a multiplexing result of the beta metrics, and calculating Log Likelihood Ratio (LLR) values corresponding to the respective shift registers at a fourth metric calculation section;
• and
• subtracting an output of the unidirectional shift register from the respective LLR values, and outputting the subtraction result for interleaving/deinterleaving at a Soft-In Soft-Out (SISO) decoder including a subtraction section.

A method of providing turbo decoding in a communication system, comprising:

• dividing input data bits into groups each comprised of bits of a predetermined length, via one or more first stage's bidirectional shift registers having a first terminal and a second terminal for data input/output, the first stage's bidirectional shift registers forming bit streams of the length by sequentially receiving and shifting bits of odd-numbered groups among the divided groups via the first terminal and then sequentially outputting the formed bit streams via the first terminal;
• and forming bit streams of the length by sequentially receiving and shifting bits of even-numbered groups among the divided groups via the second terminal and then sequentially outputting the formed bit streams via the second terminal;
• forming at a second stage's bidirectional shift register having a third terminal and a fourth terminal for data input/output, bit streams of the length by sequentially receiving and shifting bits sequentially output via the first terminal, via the third terminal, and then sequentially outputting the formed bit streams via the third terminal;
• and forming bit streams of the length by sequentially receiving and shifting bits sequentially output via the second terminal, via the fourth terminal, and then sequentially outputting the formed bit streams via the fourth terminal;
• receiving output bits of the respective shift registers, and calculating corresponding delta metrics at a first metric calculation section;
• receiving a delta metric from the first metric calculation section corresponding to a unidirectional shift register, and calculating an alpha metric at a second metric calculation section;
• receiving delta metrics from the first metric calculation section corresponding to the bidirectional shift registers, and calculating beta metrics at a third metric calculation section;
• receiving the alpha metric, also receiving a multiplexing result of the beta metrics, and calculating Log Likelihood Ratio (LLR) values corresponding to the respective shift registers at a fourth metric calculation section;
• and
• subtracting an output of a unidirectional shift register from the respective LLR values, and outputting the subtraction result for interleaving/deinterleaving at a Soft-In Soft-Out (SISO) decoder including a subtraction section.