Error notification method and information processing apparatus
AssigneeFujitsu Limited
InventorJin Takahashi
Life of this patent
Estimating the term…
Abstract
An error notification method notifies errors generated in first and second processor systems to each processor within the first and second processor systems, in a computer system that includes the first processor system operable in a normal mode and the second processor system operable together with the first processor system in a mirror mode. The error notification method generates an error interrupt signal that indicates each error by a corresponding one of a plurality of error levels, reduces the error level of a corresponding error interrupt signal when the error within the first processor system is avoided in the mirror mode, and notifies the error to each processor within the first and second processor systems using the error interrupt signal.
Claims17
An error notification method in a computer system that includes a first processing system operable in a normal mode and a second processing system operable in a mirror mode, for notifying errors generated in the first and second processor systems to each processor within the first and second processor systems, said error notification method comprising:
- generating an error interrupt signal that indicates each error by a corresponding one of a plurality of error levels;
- reducing the error level of a corresponding error interrupt signal when the error within the first processor system is avoidable in the mirror mode, and outputting an error interrupt signal in which the error level is reduced;
- and
- notifying the generated error to each processor within the first and second processor systems using the error interrupt signal.
An information processing apparatus comprising:
- a first processor system operable in a normal mode;
- a second processor system operable together with the first processor system in a mirror mode, each of the first and second processor systems comprising a storage part configured to store information indicating an internally generated error by a corresponding one of a plurality of error levels;
- a first circuit configured to receive information output from the storage part, and to generate an error interrupt signal having a corresponding error level based on the information output from the storage part;
- a second circuit configured to reduce the error level of a corresponding error interrupt signal if the error within the first processor system is avoidable in the mirror mode, and to output an error interrupt signal in which the error level is reduced;
- and
- a third circuit configured to notify the generated error to each processor within the first and second processor systems using the error interrupt signal.
An information processing apparatus, comprising:
- a first system board having a processor and configured to operate in a normal mode, and to output an error interrupt signal when an error is detected, said error interrupt signal output from the first system board indicating a level of the error detected therein;
- a second system board having a processor and configured to operate in a mirror mode, and to output an error interrupt signal when an error is detected, said error interrupt signal output from the second system board indicating a level of the error detected therein;
- and
- a third system board, coupled to the first and second system boards, and configured to receive the error interrupt signals from the first and second system boards and to notify to each of the processors of the first and second system boards the detected errors corresponding to the error levels that the received error interrupt signals indicate,
- wherein the second system board further has an error avoidance detection circuit configured to reduce a level of the detected error to an error level in which a continued operation of the information processing apparatus is permitted, and to output an error interrupt signal corresponding to the reduced error level, when it is determined that the error within the first system board is avoidable in the mirror mode.
Dependencies are inferred from the claim text.