Semiconductor integrated circuit device, debug system, microcomputer, and electronic apparatus
AssigneeSeiko Epson Corporation
InventorMakoto Kudo
Life of this patent
Estimating the term…
Abstract
An integrated circuit device including an internal debug module for on-chip debugging while communicating with a pin-saving debug tool and a CPU, the integrated circuit device comprises; a first debug terminal coupled to a first communication line; a first common control unit that controls using the first communication line for both transmission of a serial data signal corresponding debug data for sending, which is sent and/or received to and/or from the pin-saving debug tool during on-chip debugging and transmission of a run/break state signal, which shows a run state or a break state of the CPU.
Claims20
An integrated circuit device including an internal debug module for on-chip debugging while communicating with a pin-saving debug tool and a CPU, the integrated circuit device comprising:
- a debug terminal coupled to a communication line;
- a common control unit that controls using the communication line for both transmission of a serial data signal corresponding to debug data that is sent and/or received to and/or from the pin-saving debug tool during on-chip debugging and transmission of a run/break state signal, that shows a run state or a break state of the CPU, from the CPU to the pin-saving debug tool;
- the pin-saving debug tool determining whether the CPU is in the run state or the break state based on the run/break state signal received from the CPU over the communication line.
An integrated circuit device including an internal debug module for on-chip debugging while synchronously communicating with a pin-saving debug tool and a CPU, the integrated circuit device comprising;
- a debug terminal coupled to a communication line;
- a common control unit that controls using the transmission line for both transmission of a clock signal for synchronization, necessary for on-chip debugging with the pin-saving debug tool, and transmission of a run/break state signal, that shows a run state or a break state of the CPU, from the CPU to the pin-saving debug tool;
- the pin-saving debug tool determining whether the CPU is in the run state or the break state based on the run/break state signal received from the CPU over the communication line.
A debug system comprising a pin-saving debug tool and a target system, which is an object to be debugged by the debug tool, the target system having an integrated circuit device with an internal debugging module for on-chip debugging while communicating with the pin-saving debug tool, and a CPU,
- the integrated circuit device having:
- a main debug terminal coupled to a communication line;
- a main common control unit that controls using the communication line for both transmission of a serial data signal corresponding to debug data for transmission, that is sent and/or received to and/or from the pin-saving debug tool during on-chip debugging, and transmission of a run/break state signal, that shows a run state or a break state of the CPU, from the CPU to the debug tool;
- and the debug tool having:
- a sub debug terminal coupled to the communication line;
- and
- a sub common control unit that controls using the communication line for both transmission of the serial data signal corresponding to debug data for transmission, that is sent and/or received to and/or from the integrated circuit during on-chip debugging, and receipt of the run/break state signal, that shows the run state or the break state of the CPU, the debug tool determining whether the CPU is in the run state or the break state based on the run/break state signal received from the CPU over the communication line.
A debug system comprising a pin-saving debug tool and a target system, that is an object to be debugged by the debug tool, the target system comprising an integrated circuit device including an internal debugging module for on-chip debugging while communicating with the pin-saving debug tool, and a CPU, the integrated circuit device having:
- a debug terminal coupled to a communication line;
- a main common control unit that controls using the communication line for both transmission of a clock signal for synchronization, that is necessary for on-chip debugging with the pin-saving debug tool, and transmission of a run/break state signal, that shows a run state or a break state of the CPU from the CPU to the debug tool,
- the debug tool including a sub common control unit that controls using the communication line for both transmission of the clock signal for synchronization, that is necessary for on-chip debugging with the pin-saving debug tool, and receipt of the run/break state signal, that shows the run state or the break state of the CPU, the debug tool determining whether the CPU is in the run state or the break state based on the run/break state signal received from the CPU over the communication line.
Dependencies are inferred from the claim text.