Back to results
US 7,584,375 B2Granted
Active state link power management
AssigneeIntel Corporation
InventorsMichael Gutman, Alon Naveh, Andrew W. Martwick, Gary A. Solomon
Life of this patent
Estimating the term…
Abstract
A distributed power management system for a bus architecture or similar communications network. The system supports multiple low power states and defines entry and exit procedures for maximizing energy savings and communication speed.
Claims21
A method comprising:
- selecting a condition for altering a power state of a first portion of a first communication channel to a second power state, the condition selected comprising that a first portion of the first communication channel is idle for at least two symbol periods, wherein selecting is based on maximizing a period in which a link between a first device and a second device is in a low power state while reducing a frequency of exits from the second power state, wherein the second power state is a low power state with a low exit latency;
- detecting the condition in the first device, the first device coupled to the first communication channel in the first power state, the first communication channel having the first portion and a second portion;
- and
- altering the power state of the first portion of the first communication channel to the second power state, after the condition has been met for at least a predetermined period wherein the condition is that the first portion of the first communication channel that is idle for at least two symbol periods.
1 more element
A machine-readable storage medium storing information that provides instructions, which when executed by a machine cause the machine to perform operations comprising:
- selecting a condition for altering a power state of a first portion of a first communication channel to a second power state, the condition selected comprising that a first portion of the first communication channel is idle for at least two symbol periods, wherein selecting is based on maximizing a period in which a link between a first device and a second device is in a low power slate while reducing a frequency of exits from the second power state, wherein the second power state is a low power state with a low exit latency;
- detecting the condition in the first device, the first device coupled to the first communication channel in an first power state, the first communication channel having a first portion and a second portion;
- and
- altering the power state of the first portion of the first communication channel to the second power state, after the condition has been met for at least a predetermined period wherein the condition is that the first portion of the first communication channel that is idle for at least 2 symbol periods.
1 more element
Dependencies are inferred from the claim text.