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US 7,584,369 B2Granted
Method and apparatus for monitoring and controlling heat generation in a multi-core processor
AssigneeInternational Business Machines Corporation
InventorsLouis Bennie Capps, Jr., Warren D. Dyckman, Michael Jay Shapiro
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Abstract
The disclosed methodology and apparatus may control heat generation in a multi-core processor. In one embodiment, each processor core includes a temperature sensor that reports temperature information to a processor controller. If a particular processor core exceeds a predetermined temperature, the processor core disables that processor core to allow it to cool. The processor core enables the previously disabled processor when the previously disabled processor core cools sufficiently to a normal operating temperature. The disclosed multi-core processor may avoid undesirable hot spots that impact processor life.
Claims15
A method of controlling heat generation in a processor, the method comprising:
- receiving power by a processor that includes a plurality of processor cores on a common semiconductor die, each processor core being enabled or disabled;
- disabling first selected processor cores, by a core power controller, during a first power control time interval while other processor cores remain enabled, the first power control time interval exhibiting a predetermined period of time;
- disabling second selected processor cores, by the core power controller, during a second power control time interval following the first power control time interval, the second selected processor cores of the second power control time interval being different from the first selected processor cores of the first power control time interval;
- disabling other selected processor cores, by the core power controller, during successive power control time intervals that follow the second power control time interval to form a complete cycle wherein all processor cores have been disabled once;
- sensing, by a thermal sensor in each processor core, the temperature of each processor core;
- receiving, by the core power controller, temperature information from the temperature sensor of each processor core;
- and
- controlling the processor cores, by the core power controller, to disable those processor cores whose temperatures exceed a first predetermined temperature value.
5 more elements
A processor comprising:
- a plurality of processor cores situated on a semiconductor die, each processor core including a respective temperature sensor that senses the temperature thereof;
- and
- a core power controller, coupled to the plurality of processor cores, situated on the semiconductor die, the core power controller being capable of receiving temperature information from each processor core, the core power controller disabling the processor cores whose temperatures exceed a first predetermined temperature value, the core power controller disabling first selected processor cores during a first power control time interval while other processor cores remain enabled, the core power controller disabling second selected processor cores during a second power control time interval following the first power control time interval, the second selected processor cores of the second power control time interval being different from the first selected processor cores of the first power control time interval, the core power controller disabling other selected processor cores during successive power control time intervals that follow the second time power control interval to form a complete cycle wherein all processor cores have been disabled once.
An information handling system (IHS) comprising:
- a memory;
- a processor, coupled to the memory, the processor including:
- a plurality of processor cores situated on a semiconductor die, each processor core including a respective temperature sensor that senses the temperature thereof;
- and
- a core power controller, coupled to the plurality of processor cores, situated on the semiconductor die, the core power controller being capable of receiving temperature information from each processor core, the core power controller disabling the processor cores whose temperatures exceed a first predetermined temperature value, the core power controller disabling first selected processor cores during a first power control time interval while other processor cores remain enabled, the core power controller disabling second selected processor cores during a second power control time interval following the first power control time interval, the second selected processor cores of the second power control time interval being different from the first selected processor cores of the first power control time interval, the core power controller disabling other selected processor cores during successive power control time intervals that follow the second power control time interval to form a complete cycle wherein all processor cores have been disabled once.
2 more elements
Dependencies are inferred from the claim text.