Methods and arrangements for hybrid data storage
AssigneeInternational Business Machines Corporation
InventorScott L. Daniels
Life of this patent
Estimating the term…
Abstract
Embodiments may comprise a hybrid memory controller to facilitate accesses of more than on type of memory device, referred to generally hereafter as a hybrid memory device or hybrid cache device. The hybrid memory controller may include split logic to determine whether to split data of a write request into more than one portion and to store each portion in a different type of data storage device. For example, one embodiment comprises a hybrid memory controller to store data in both SRAM and DRAM devices. The SRAM and DRAM devices may include distinct circuits on a die, distinct dies within a chip, distinct chips on a memory module, distinct memory modules, or the like.
Claims19
A method to store data in memory, the method comprising:
- identifying, by a memory controller, a first portion of the data associated with a write request;
- storing, by the memory controller, the first portion of the data in a first memory device;
- storing, by the memory controller, a second portion of the data in a second memory device, the first memory device having an initial access latency that is shorter than an initial access latency of the second memory device, wherein memory locations of the first portion and the second portion have consecutive memory addresses;
- receiving a read request for the data;
- accessing, by the memory controller, the first memory device to retrieve the first portion of the data;
- accessing, by the memory controller, the second memory device to retrieve a second portion of the data during the accessing of the first memory device;
- and
- transmitting the first and second portions of the data in response to the read request.
An apparatus to store data, the apparatus comprising:
- a first type of memory device;
- a second type of memory device;
- and
- a memory controller coupled with the first type of memory device and the second type of memory device, the memory controller to be responsive to a write request to write data associated with the write request to the first type of memory device and the second type of memory device and responsive to a read request for the data to read a first portion of the data from the first type of memory device during an initial latency associated with access to a second portion of the data in the second type of memory device, to read the second portion of the data in the second type of memory device during the read of the first portion of the data from the first type of memory device, and to transmit the first and second portions of the data in response to the read request, wherein memory locations for the first portion of the data and the second portion of the data are assigned consecutive memory addresses.
A system for hybrid memory storage, the system comprising:
- a processor;
- a static random access memory (SRAM) device;
- a dynamic random access memory (DRAM) device;
- and
- a memory controller coupled with the processor via a bus to store data of a write request from the processor in the SRAM and DRAM devices, wherein the memory controller comprises logic to split the data into at least a first portion to store in the SRAM device and a second portion to store in the DRAM device, and, in response to a read request for the data, to read the first portion of the data from the SRAM device and to read the second portion of the data form the DRAM device during the read of the first portion of the data from the SRAM device, and to transmit the first and second portions of the data in response to the read request, memory locations of the first portion and the second portion to have consecutive memory addresses.
A device to couple with a memory controller, the device comprising:
- a first memory device with a low initial access latency;
- a second memory device with a high initial access latency;
- and
- address-decoding logic interconnected with the first memory device and the second memory device, the address-decoding logic to associate a first, consecutive physical address range with the first memory device and a second, consecutive physical address range with the second memory device, wherein the first, consecutive physical address range is consecutive with the second, consecutive physical address range, wherein the address-decoding logic is responsive to a write command to write data from the memory controller to the memory devices, the address-decoding logic to decode an address of the write command to write a first portion of the data to the first memory device and a second portion of the data to the second memory device, and the address-decoding logic is responsive to a read command for the data from the memory controller to decode an address of the read command to read the first portion of the data from the first memory device and to read the second portion of the data from the second memory device, to transmit the data to the memory controller.
Dependencies are inferred from the claim text.