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US 7,584,332 B2Granted
Computer systems with lightweight multi-threaded architectures
AssigneesUniversity of Notre Dame du Lac, Cray Inc.
InventorsPeter M. Kogge, Jay B. Brockman, David Tennyson Harper, III, Burton Smith, Charles David Callahan, II
Life of this patent
Estimating the term…
Abstract
Embodiments of the present invention provide a class of computer architectures generally referred to as lightweight multi-threaded architectures (LIMA). Other embodiments may be described and claimed.
Claims66
A method comprising:
- processing, by one of a memory controller or a memory interface within a lightweight multi-threaded architecture (LIMA) computing system, a request to access a memory location by a program thread being executed by a processor within the LIMA computing system;
- evaluating, by the one of a memory controller or a memory interface, an extension field of the memory location to determine a state of a value field of the memory location;
- and
- accessing, by the program thread, the value field based upon said evaluating an extension field.
1 more element
A method comprising:
- executing, by a lightweight processor (LWP) of a lightweight multi-threaded architecture (LIMA) computing system, at least one program thread, wherein the LWP includes a pool of information defining one or more separate program threads, each of which has associated with it a frame comprising one or more unique registers that a thread's program may manipulate;
- deciding, by the LWP, which thread to allow to execute an instruction from that thread's program;
- and
- also deciding, by the LWP, when it is appropriate to evict a frame and/or bring in a new frame corresponding to a different thread than any currently executing.
1 more element
A computing system comprising:
- one or more nodes, each node comprising at least one lightweight processing chip (LPC) that includes a lightweight processor (LWP) core and at least one memory module, each node being adapted to concurrently execute a number of independent program threads on behalf of one or more application programs, and each thread being adapted to generate one or more requests to access memory anywhere in the computing system;
- an interconnect network communicatively coupling multiple nodes such that LPCs within a node may issue a memory or thread creation request that may be routed to a node that includes designated memory locations and return one of a copy of the data or completion status back to a requesting LPC;
- an internal node routing system adapted to facilitate memory requests between LPCs within a node and to facilitate communication with the interconnect network for memory requests elsewhere within the computing system;
- and
- memory within the computing system that is external to the nodes;
- wherein each LPC is adapted to receive memory requests and are adapted to generate memory requests.
3 more elements
A computing system comprising:
- one or more nodes, each node comprising at least one lightweight processing chip (LPC) that includes a lightweight processor (LWP) core and at least one memory module, each node being adapted to concurrently execute a number of independent program threads on behalf of one or more application programs, and each thread being adapted to generate one or more requests to access memory anywhere in the computing system;
- an interconnect network communicatively coupling multiple nodes such that LPCs within a node may issue a memory or thread creation request that may be routed to a node that includes designated memory locations and return one of a copy of the data or completion status back to a requesting LPC;
- and
- at least one heavyweight processor (HWP) communicatively coupled to the interconnect network and adapted to generate streams of memory reference requests;
- wherein the at least one HWP does not include program visible memory.
2 more elements
A massively parallel computing system comprising:
- one or more nodes, each node comprising at least one lightweight processing chip (LPC) that includes a lightweight processor (LWP) core and at least one memory module, each node being adapted to concurrently execute a number of independent program threads on behalf of one or more application programs, and each thread being adapted to generate one or more requests to access memory anywhere in the computing system;
- and
- an interconnect network communicatively coupling multiple nodes such that LPCs within a node may issue a memory or thread creation request that may be routed to a node that includes designated memory locations and return one of a copy of the data or completion status back to a requesting LPC.
A computing system comprising:
- one or more nodes, each node comprising at least one lightweight processing chip (LPC) that includes a lightweight processor (LWP) core and at least one memory module, each node being adapted to concurrently execute a number of independent program threads on behalf of one or more application programs, and each thread being adapted to generate one or more requests to access memory anywhere in the computing system;
- and
- an interconnect network communicatively coupling multiple nodes such that LPCs within a node may issue a memory or thread creation request that may be routed to a node that includes designated memory locations and return one of a copy of the data or completion status back to a requesting LPC;
- wherein at least some of the LPCs include multiple memory modules;
- and
- wherein at least some of the LPCs include multiple LWPs.
3 more elements
Dependencies are inferred from the claim text.